BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 445

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Internal SCL output
(Master A)
Internal SCL output
(Master B)
SCL line
3.14.6.4 Master/Slave Selection
(2) Clock synchronization
detected on the bus.
detecting this situation, Master B resets the high level period count and pulls I2C0CL
low.
Since Master B is still holding the SCL line low, Master A does not start counting the
high level period. Master A starts counting the high level period after Master B sets
I2C0CL to high at point “c” and the SCL line of the bus becomes high.
line of the bus becomes low.
When I2C0CR2<MST> is set to 1, I
When I2C0CR2<MST> is cleared to 0, it is configured as a slave device.
I2C0SR<MST> is cleared to 0 by hardware when a stop condition or arbitration lost is
high level period and the master device with the longest low level period among master
devices connected to the bus.
down the clock line low invalidates the clock outputs from other masters on the bus.
Masters who are keeping the clock line high need to detect this situation and act as
required.
when multiple masters exist on the bus.
masters simultaneously exist on the bus.
As Master A pulls I2C0CL low at point “a”, the SCL line of the bus becomes low. After
Master A finishes counting the low level period at point “b” and sets I2C0CL to high.
Then, after counting the high level period, Master A pulls I2C0CL low and the SCL
The clock operation on the bus is determined by the master device with the shortest
The I
I
The clock synchronization procedure is explained below using an example where two
2
C has a clock synchronization function to ensure proper transfer operation even
2
C bus is driven by the wired AND method, and a master device that first pulls
Figure 3.14.14 Example of clock synchronization
a
High period
count reset
TENTATIVE
TMPA900CM- 444
High period
count standby
2
b
C is configured as a master device.
c
High period count start
TMPA900CM
2009-10-14