BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 293

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(3) SMC Function
(a) APB slave I/F
(b) Format
(c) Memory manager operation
(d) Chip configuration registers
(e) Memory I/F operation
1. hazard
2. Access to the SRAM memory
mode memory. No burst align settings are necessary for Nor Flash.
configuration registers.
registers by using the following two methods:
•
•
•
•
•
•
•
• Outstanding direct commands.
• A memory command is received, but the previous memory command has not
The burst align settings are necessary in order to support asynchronous page
The memory manager controls the SMC state and manages update of chip
A function that synchronizes with switching of SMC operational modes
Direct commands
The SMC supports updating of the controller and memory configuration
• Control by using memory device pins
• Software mechanism: Control by sequence requests by read/write commands
The memory I/F issues commands and control their timings.
The APB slave I/F adds a wait state for all reads and writes
More than one wait stat is generated in the following cases:
Memory burst length: The supported memory burst transfer length is from 1 to
Booting using the SRAM: The lowest RAM CS (generally RAM CS0) can be
been completed.
Read After Read (RAR)
Write After Write (WAW)
Read After Write (RAW)
Write After Read (WAR)
Standard SRAM access
Memory address shifting
Memory burst alignment
TENTATIVE
TMPA900CM- 292
32 beats. A continuous burst is also supported. However,
the length of burst transfer is limited by the size of read
and write data FIFOs. The burst length of read and write
data is 4.
booted.
TMPA900CM
2009-10-14