M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 132

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
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11.3 Hardware Interrupts
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Special interrupts and peripheral function interrupts are available as hardware interrupts.
11.3.1 Special Interrupts
11.3.2 Peripheral Function Interrupt
1
9
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B
Special interrupts are non-maskable interrupts.
0
1
11.3.1.1 NMI Interrupt
11.3.1.2 Watchdog Timer Interrupt
11.3.1.3 Oscillation Stop Detection Interrupt
11.3.1.4 Low Voltage Detection Interrupt
11.3.1.5 Single-Step Interrupt
11.3.1.6 Address Match Interrupt
4
0
The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal
to a low-level ("L") signal. Refer to 11.8 NMI Interrupt for details.
The watchdog timer interrupt occurs when a count source of the watchdog timer underflows. Refer to
12. Watchdog Timer for details.
The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscilla-
tion stop. Refer to 9. Clock Generation Circuit for details.
The low voltage detection interrupt occurs when the voltage applied to V
Refer to 6. Voltage Detection Circuit for details.
NOTES:
Do not use the single-step interrupt. For development support tool only.
The address match interrupt occurs immediately before executing an instruction that is stored into an
address indicated by the RMADi register (i=0 to 7) when the AIERi bit in the AIER register is set to "1"
(address match interrupt enabled). Set the starting address of the instruction in the RMADi register.
The address match interrupt does not occur when a table data or addresses of the instruction other
than the starting address, if the instruction has multiple addresses, is set. Refer to 11.10 Address
Match Interrupt for details.
The peripheral function interrupt occurs when a request from the peripheral functions in the microcom-
puter is acknowledged. The peripheral function interrupts and software interrupt numbers 8 to 48, 52
to 54 and 57 for the INT instruction use the same interrupt vector table. The peripheral function inter-
rupt is a maskable interrupt.
See Table 11.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each
function for details.
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1. Low voltage detection interrupt cannot be used in M32C/84T.
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Page 109
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9
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______
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CC1
is above or below Vdet4.
11. Interrupts