M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 330

• Manufacturer Part Number: M30845FJGP#U3
• Description: IC M32C MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30845FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
3
. v
J
2
Figure 22.27 G1IRF Register, G0TB and G1TB / G0DR and G1DR Registers
0
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
SI/O Special Communication Interrupt Detect Register 1
o r
0 -
. l
Transmit Buffer (Receive Data) Register
b7
b7
NOTES:
u
0
1
p
, 7
0
b6
1. The G1IRF register is used in special communication mode or HDLC data processing mode. It must
2. The SRT1R bit in the IIO4IR register is also set to "1" if the BSERR, ABT or IRF0 to IRF3 bit is set to "1".
1
(
2
be in a reset state or set to "00
M
b5
0
3
0
2
5
b4
C
8 /
b3
Page 307
, 4
b2
M
0
b1
3
2
C
0
b0
b0
f o
8 /
(b1 - b0)
Set data to be transmitted.
In HDLC data processing mode, the receive data register is read by
reading the GiTB register. Value is written to the transmit buffer register
by writing it to the GiTB register. In HDLC data processing mode, the
value set in the GiRI register is transferred to the GiDR register.
4
4
BSERR
Symbol
) T
9
IRF0
IRF1
IRF2
IRF3
ABT
Bit
5
Symbol
G1IRF
Symbol
G0TB, G0DR
G1TB, G1DR
16
Reserved Bit
Bit Stuffing Error
Detect Flag
Arbitration Lost
Detect Flag
Interrupt Cause
Determination
Flag 0
Interrupt Cause
Determination
Flag 1
Interrupt Cause
Determination
Flag 2
Interrupt Cause
Determination
Flag 3
" in clock synchronous serial I/O mode or UART mode.
Bit Name
Address
013E
Address
00EA
012A
16
16
16
0 : The G1DR register (receive data register)
1 : The G1DR register (receive data register)
0 : The G1DR register (receive data register)
1 : The G1DR register (receive data register)
0 : The G1DR register (receive data register)
1 : The G1DR register (receive data register)
0 : The G1DR register (receive data register)
1 : The G1DR register (receive data register)
0 : Not detected
1 : Detected
0 : Not detected
1 : Detected
Set to "0"
does not match the G1CMP0 register
matches the G1CMP0 register
does not match the G1CMP1 register
matches the G1CMP1 register
does not match the G1CMP2 register
matches the G1CMP2 register
does not match the G1CMP3 register
matches the G1CMP3 register
Function
(i=0,1)
22. Intelligent I/O (Communication Function)
Function
After Reset
Indeterminate
After Reset
00
Indeterminate
16
(1,2)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW