M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 153

• Manufacturer Part Number: M30845FJGP#U3
• Description: IC M32C MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30845FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
2
Figure 11.15 IIO0IE to IIO4IE, IIO8IE to IIO11IE Registers
0
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
Interrupt Enable Register
u
Bit Symbols for the Interrupt Enable Register
BT1E
TM1jE
PO1jE
SIOiRE
SIOiTE
GiRIE
GiTOE
SRTiE
CAN0kE
-
b7
o r
0 -
. l
Symbol
IIO10IE
IIO11IE
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
IIO8IE
IIO9IE
u
0
1
b6
, 7
0
p
NOTES:
1
(
b5
2
M
1. See table below for bit symbols.
2. If an interrupt request is used for interrupt, set bit 1, 2, 4 to 7 to "1" after the IRLT bit is set to "1".
0
0
3
Address
b4
: Intelligent I/O Base Timer Interrupt Enabled
: Intelligent I/O Time Measurement j Interrupt Enabled
: Intelligent I/O Waveform Generating Function j Interrupt Enabled
: Intelligent I/O Communication Unit i Receive Interrupt Enabled
: Intelligent I/O Communication Unit i Transmit Interrupt Enabled
: Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Enabled (RI: Output to Receive)
: Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Enabled (TO: Input to Transmit)
: Intelligent I/O Special Communication Function Interrupt Enabled
: CAN0 Communication Function Interrupt Enabled (k = 0 to 2)
: Reserved Bit. Set to "0".
00BA
00BB
00B0
00B1
00B2
00B3
00B4
00B8
00B9
5
2
C
b3
0
8 /
Page 130
16
16
16
16
16
16
16
16
16
, 4
b2
CAN00E
CAN01E
CAN02E
M
SRT0E
b1
Bit 7
3
-
-
-
-
-
2
b0
C
f o
8 /
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
4
Symbol
4
IRLT
(b3)
SRT 1E
) T
9
Bit
Bit 6
5
Symbol
IIO0IE to IIO4IE, IIO8IE to IIO11IE
-
-
-
-
-
-
-
-
Interrupt Request
Select Bit
Reserved Bit
SIO0RE
SIO1RE
SIO0TE
SIO1TE
Bit 5
Bit Name
-
-
-
-
-
(2)
G0TOE
G1TOE
G0RIE
G1RIE
BT1E
Bit 4
-
-
-
-
Set to "0"
0 : Interrupt request is used for DMAC, DMAC II
1 : Interrupt request is used for interrupt
0 : Disables an interrupt by bit 1 in IIOiIR register
1 : Enables an interrupt by bit 1 in IIOiIR register
0 : Disables an interrupt by bit 2 in IIOiIR register
1 : Enables an interrupt by bit 2 in IIOiIR register
0 : Disables an interrupt by bit 4 in IIOiIR register
1 : Enables an interrupt by bit 4 in IIOiIR register
0 : Disables an interrupt by bit 5 in IIOiIR register
1 : Enables an interrupt by bit 5 in IIOiIR register
0 : Disables an interrupt by bit 6 in IIOiIR register
1 : Enables an interrupt by bit 6 in IIOiIR register
0 : Disables an interrupt by bit 7 in IIOiIR register
1 : Enables an interrupt by bit 7 in IIOiIR register
Bit 3
-
-
-
-
-
-
-
-
-
Address
See below
TM13E/PO13E
TM14E/PO14E
TM12E/PO12E
TM10E/PO10E
TM17E/PO17E
Bit 2
-
-
-
-
Function
After Reset
0000 0000
TM15E/PO15E
TM16E/PO16E
TM11E/PO11E
Bit 1
2
-
-
-
-
-
-
i = 0, 1
j = 0 to 7
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
Bit 0
RW
RW
RW
RW
RW
RW
RW
RW
RW
11. Interrupts