M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 316

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Table 22.9 Single-Phase Waveform Output Mode Specifications
Waveform Output Start Condition
Waveform Output Stop Condition
Interrupt Request
OUTC1j Pin
Selectable Function
NOTES:
C
Output Waveform
22.3.1 Single-Phase Waveform Output Mode
1
9
0 .
8 /
B
Output signal level of the OUTC1j pin becomes high ("H") when the value of the base timer matches that
of the G1POj register (j=0 to 7). The "H" signal swithches to a low-level ("L") signal when the base timer
reaches "0000
signal output is provided when waveform output starts. If the INV bit is set to "1" (output inversed), the
level of the waveform output is inversed. See Figure 22.16 for details on single-phase waveform output
mode operation. Table 22.9 lists specifications of single-phase waveform output mode.
1. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected).
2. When the INV bit in the G1POCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed.
0
1
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
Item
1
(
2
M
0
3
0
(2)
2
5
16
C
". If the IVL bit in the G1POCRj register is set to "1" ("H" output as default value), an "H"
8 /
Page 293
, 4
M
3
2
C
(1)
f o
8 /
4
4
The IFEj bit in the G1FE register is set to "1" (channel j function enabled)
) T
• Free-running operation
• The base timer is cleared to "0000
The IFEj bit is set to "0" (channel j function disabled)
The PO1jR bit in the interrupt request register is set to "1" (interrupt
requested) when the value of the base timer matches that of the G1POj
register. (See Figure 11.14)
Pulse signal output pin
• Default value set function: Set starting waveform output level
• Inversed output function:
9
Cycle
5
(the RST2 and RST1 bits in the G1BCR1 register are set to "00
"L" width
"H" width
G1PO0 register (the RST1 bit is set to "1" and the RST2 bit is set to "0")
Cycle
"L" width
"H" width
Waveform output signal is inversed and provided from the OUTC1j pin
m : setting value of the G1POj register (j=0 to 7), 0000
m : setting value of the G1POj register (j=1 to 7), 0000
n : setting value of the G1PO0 register, 0001
If m
n+2, the output level is fixed to "L"
:
:
:
:
:
:
65536-m
n+2-m
65536
n+2
f
f
f
f
m
f
f
BT1
BT1
BT1
m
BT1
BT1
BT1
22. Intelligent I/O (Waveform Generating Function)
Specification
16
" by matching the base timer with the
16
to FFFD
16
16
16
to FFFF
to FFFF
2
")
16
16