M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 372

• Manufacturer Part Number: M30845FJGP#U3
• Description: IC M32C MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30845FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
3
. v
J
2
Figure 23.23 C0GMR1, C0LMAR1 and C0LMBR1 Registers
0
C
1
9
8 /
0 .
B
0
1
4
0
G
3
J
6
u
o r
0 -
. l
CAN0 Global Mask Register Standard ID1
CAN0 Local Mask Register A Standard ID1
CAN0 Local Mask Register B Standard ID1
b7
u
0
1
NOTES:
p
, 7
0
b6
1
(
1. The C0GMR0, C0LMAR0 and C0LMBR0 registers can be accessed only when the BANKSEL bit in
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after
3. The C0LMAR1 register shares the same address with the C0MCTL1 register.
4. The C0LMBR1 register shares the same address with the C0MCTL9 register.
2
M
0
b5
the C0CTLR1 register is set to "1" (mask register selected).
reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0".
3
0
2
5
b4
C
8 /
Page 349
b3
, 4
b2
M
3
b1
2
C
b0
8 /
f o
4
(b7 - b6)
4
Symbol
SID0M
SID1M
SID2M
SID3M
SID4M
SID5M
) T
9
5
Bit
Symbol
C0GMR1
C0LMAR1
C0LMBR1
Standard ID0
Standard ID1
Standard ID2
Standard ID3
Standard ID4
Standard ID5
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
Address
0229
0231
0239
16
16 (3)
16
(1)
0: No ID is verified
1: ID is verified
(1)
(4)
(1)
Function
After Reset
XX00 0000
XX00 0000
XX00 0000
2
2
2
(2)
23. CAN Module
RW
RW
RW
RW
RW
RW
RW