M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 137

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
11.6 Interrupt Request Acknowledgement
e
E
3
. v
J
2
Table 11.3 Interrupt Priority Levels
0
C
Software interrupts and special interrupts occur when conditions to generate an interrupt are met.
The peripheral function interrupts are acknowledged when all conditions below are met.
• I flag
• IR bit
• ILVL2 to ILVL0 bits
The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the
FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register.
11.6.1 I Flag and IPL
11.6.2 Interrupt Control Register and RLVL Register
1
9
0 .
8 /
B
The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable
interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically
set to "0" after reset.
IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7.
If a requested interrupt has higher priority level than indicated by IPL, the interrupt is acknowledged.
Table 11.3 lists interrupt priority levels associated with IPL.
IPL2
The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 11.3
and 11.4 show the interrupt control register. Figure 11.5 shows the RLVL register.
0
1
4
0
0
0
0
1
1
1
1
0
3
G
J
6
u
o r
0 -
. l
u
0
1
, 7
0
p
1
(
2
M
0
IPL1
0
3
0
0
1
1
0
0
1
1
5
2
C
8 /
Page 114
, 4
M
IPL0
1
3
0
1
0
1
0
1
0
2
C
= "1"
= "1"
> IPL
f o
8 /
4
4
) T
9
5
Level 1 and above
Level 2 and above
Level 3 and above
Level 4 and above
Level 5 and above
Level 6 and above
Level 7 and above
All maskable interrupts are disabled
Interrupt Priority Levels
11. Interrupts