M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 233

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
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3
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2
Table 17.7 Register Settings in UART Mode
0
NOTES:
C
Table 17.7 lists register settings. Tables 17.8 to 17.10 list pin settings. When UARTi (i=0 to 4) operating
mode is selected, the TxDi pin outputs a high-level ("H") signal before transfer is started (the TxDi pin is in
a high-impedance state when the N-channel open drain output is selected). Figure 17.14 shows an ex-
ample of a transmit operation in UART mode. Figure 17.15 shows an example of a receive operation in
UART mode.
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
1
9
Register
0 .
8 /
B
1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long.
0
1
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
1
8 to 0
8 to 0
OER, FER,
PER, SUM
7 to 0
SMD2 to SMD0
CKDIR
STPS
PRY, PRYE
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS
UiRRM
UiLCH
UiERE
7 to 0
7 to 0
7 to 0
7 to 0
(
2
M
0
3
0
2
5
C
Bit
8 /
Page 210
, 4
M
3
2
C
f o
8 /
Set transmit data
Received data can be read
Error flags
Set bit rate
Set to "100
Set to "101
Set to "110
Select the internal clock or external clock
Select stop bit length
Select parity enable or disable, odd or even
Select TxD and RxD I/O polarity
Select count source for the UiBRG register
Select either CTS or RTS when using either
Transfer register empty flag
Enables or disables the CTS or RTS function
Select output format of the TxDi pin
Set to "0"
Select the LSB first or MSB first when a transfer data is 8 bits long
Set to "0" when transfer data is 7 bits or 9 bits long
Set to "1" to enable data transmission
Transfer buffer empty flag
Set to "1" to enable data reception
Reception complete flag
Select what causes the UARTi transmit interrupt to be generated
Set to "0"
Select whether data logic is inversed or not inversed when a transfer data is
7 bits or 8 bits long. Set to "0" when transfer data is 9 bits long
Set to either "0" or "1"
Set to "00
Set to "00
Set to "00
Set to "00
4
4
) T
9
5
16
16
16
16
2
2
2
"
"
"
"
" when transfer data is 7 bits long
" when transfer data is 8 bits long
" when transfer data is 9 bits long
_______
(1)
_______
________
(1)
Function
_______
17. Serial I/O (UART)