M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 313

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
e
E
3
. v
J
2
0
Figure 22.14 Time Measurement Function (2)
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
o r
(1)
(3) Trigger signal when using the digital filter
0 -
(2)
. l
u
0
1
Base timer
INPC1j pin
TM1jR bit
G1TMj register
Base timer
INPC1j pin
G1TMj register
INPC1j pin
f
f
TM1jR bit
f1 or f
Trigger signal
after passing
the digital filter
BT1
BT1
p
, 7
0
When selecting the rising edge as a time measurement trigger
When selecting both edges as a time measurement trigger
(The DF1 and DF0 bits in the G1TMCRj register are set to "10
(The CTS1 and CTS0 bits are set to "11
1
(The CTS1 and CTS0 bits in the G1TMCRj register (j=0 to 7) are set to "01
(
2
M
BT1
0
3
0
NOTES:
NOTES:
NOTES:
(1)
5
2
(1)
(1)
1. Bits in the IIO0IR to IIO4IR, IIO08IR to IIO10R registers. See Figure 11.14 about the TM1jR bit.
2. No interrupt is generated if the microcomputer receives a trigger signal when the TM1jR bit is set to "1".
1. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. See Figure 11.14 about the TM1jR bit.
2. Input pulse applied to the INPC1j pin requires 1.5 f
C
1. f
However, the value of the G1TMj register changes.
8 /
Page 290
BT1
, 4
when the DF1 and DF0 bits are set to "10
"H"
"L"
M
"H"
"L"
"H"
"L"
"1"
"0"
"H"
"L"
"1"
"0"
3
2
C
n-2
n-2
f o
8 /
4
4
n-1
n-1
) T
9
5
n
n
Delayed by max. 1 clock
Signal, which does not match
three times, is stripped off
n+1
n+1
n
n+2
n+2
n
n+3
n+3
n+2
2
n+4
n+4
2
(Note 2)
")
", and f
BT1
n+5 n+6
n+5
n+5
clock cycles or more.
1
when to "11
(Note 2)
n+6
22. Intelligent I/O (Time Measurement Function)
n+5
n+6
n+7
n+7
n+8
n+8
2
".
The trigger signal is delayed
by the digital filter
n+9 n+10 n+11 n+12 n+13 n+14
n+9 n+10 n+11 n+12 n+13 n+14
2
Write "0" by program
if setting to "0"
" or "11
n+8
n+8
2
Maximum 3.5 f1 or
f
BT1 (1)
")
clock cycles
2
")
n+12
Write "0" by program
if setting to "0"