M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 249

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
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17.4 Special Mode 2
3
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J
2
Table 17.19 Special Mode 2 Specifications
0
C
NOTES:
In special mode 2, serial communication between one or multiple masters and multiple slaves is available.
The SSi input pin (i=0 to 4) controls the serial bus communication. Table 17.19 lists specifications of special
mode 2. Table 17.20 lists register settings. Tables 17.21 to 17.23 list pin settings.
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmit Start Condition To start transmitting, the following requirements must be met
Receive Start Condition To start receiving, the following requirement must be met
Error Detection
1
9
Interrupt Request
Generation Timing
Selectable Function
8 /
0 .
B
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the
3. If an overrun error occurs, the UiRB register is in an indeterminate state. The IR bit in the SiRIC register does not
0
1
4
0
CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data
is received on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is
transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is
held low ("L").
change to "1" (interrupt requested).
_____
G
3
J
6
u
o r
0 -
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Item
u
0
1
p
, 7
0
1
(
2
M
0
3
0
2
5
C
8 /
Page 226
, 4
______
Transfer data : 8 bits long
• The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected):
• The CKDIR bit to "1" (external clock selected) : input from the CLKi pin
SSi input pin function
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
• Overrun error
M
• While transmitting, the following conditions can be selected:
• While receiving
• Fault error
• CLK polarity
• LSB first or MSB first
• Continuous receive mode
• Serial data logic inverse
• TxD and RxD I/O polarity inverse
• Clock phase
• SSi input pin function
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) :
- The UiIRS register is set to "1" (transmission completed):
when data is transferred from the UiTB register to the UARTi transmit register (transmission started)
_____
3
when data transmission from UARTi transfer register is completed
In master mode, the fault error occurs an "L" signal is applied to the SSi pin
the UiRB register
This error occurs when the seventh bit of the next received data is read before reading
Select from the rising edge or falling edge of the transfer clock when transferred data
is output and input are provided
Data is transmitted or received in either bit 0 or in bit 7
Reception is enabled simultaneously by reading the UiRB register
This function inverses transmitted or received data logically
TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
Select from one of 4 combinations of transfer data polarity and phases
Output pin is placed in a high-impedance state to avoid data conflict between master
and other masters or slaves
2
C
f
j
/2(m+1) f
8 /
f o
4
4
) T
9
5
(3)
j
= f
1
, f
8
, f
2n (1)
m
: setting value of the UiBRG register, 00
Specification
(2)
17. Serial I/O (Special Function)
:
(2)
:
______
16
to FF
16