M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 253

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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3
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2
Figure 17.24 Transmit and Receive Timing in Master Mode (Internal Clock)
0
C
17.4.2 Clock Phase Setting Function
1
9
8 /
0 .
B
The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four
combinations of transfer clock polarity and phases.
The transfer clock phase and polarity must be the same between the master and the slave involved in the
transfer.
0
1
4
17.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))
17.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))
0
G
3
Figure 17.24 shows transmit and receive timing.
When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin
is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a
serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the
transfer clock. Figure 17.25 shows the transmit and receive timing.
When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high, the STxDi pin is placed
in a high-impedance state. When the SSi pin becomes low, the first data is output. The serial transmis-
sion is synchronized with the transfer clock. Figure 17.26 shows the transmit and receive timing.
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6
u
o r
0 -
. l
u
0
1
Data Output Timing
Data Input Timing
Signal Applied to
the SS Pin
Clock Output
(CKPOL=0, CKPH=0)
Clock Output
(CKPOL=1, CKPH=0)
Clock Output
(CKPOL=0, CKPH=1)
Clock Output
(CKPOL=1, CKPH=1)
p
, 7
0
1
(
2
M
0
3
0
2
5
C
8 /
Page 230
, 4
M
3
2
C
"H"
"L"
"H"
"L"
8 /
"H"
"L"
"H"
"L"
"H"
"L"
f o
"H"
"L"
4
4
) T
9
5
D
0
_____
D
1
D
_____
2
_____
D
3
_____
D
4
D
5
17. Serial I/O (Special Function)
D
6
D
7