M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 150

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
11.11 Intelligent I/O Interrupt and CAN Interrupt
e
E
3
. v
J
2
Figure 11.13 Intelligent I/O Interrupt and CAN Interrupt
0
C
The intelligent I/O interrupt and CAN interrupt are assigned to software interrupt numbers 44 to 48, 52 to 54,
and 57.
When using the intelligent I/O interrupt or CAN interrupt, set the IRLT bit in the IIOiIE register (i = 0 to 4, 8
to 11) to "1" (interrupt request for interrupt used).
Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is gener-
ated with each intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1"
(interrupt requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled), the
IR bit in the corresponding IIOiIC register is set to "1" (interrupt requested).
After the IR bit setting changes "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register is set
to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1".
Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each bit
to "0" by program. If these bit settings are left "1", all generated interrupt requests are ignored.
Figure 11.13 shows a block diagram of the intelligent I/O interrupt and CAN interrupt. Figure 11.14 shows
the IIOiIR register. Figure 11.15 shows the IIOiIE register.
1
9
0 .
8 /
B
Interrupt Request
Interrupt Request
Interrupt Request
0
1
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
0
3
5
2
(1)
(1)
(1)
C
8 /
Page 127
IIOiIR Register
, 4
IIOiIE Register
M
Bit 1
Bit 2
Bit 7
Bit 1
Bit 2
Bit 7
3
2
C
f o
8 /
4
4
(2)
) T
9
(3)
5
IRLT Bit in
IIOiIE Register
0
1
0
1
0
1
NOTES:
i= 0 to 4, 8 to 11
1. See Figures 11.14 and 11.15 about bits 1 to 7 in the
2. Bits 1 to 7 in the IIOiIR register are not set to "0"
3. Do not change the IRLT bit and the interrupt enable bit
IIOiIR register and bits 1 to 7 in the IIOiIE register.
automatically even if an interrupt request is
generated. Set to "0" by program.
in the IIOiIE register simultaneously.
Intelligent I/O Interrupt i Request
11. Interrupts