M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 243

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
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J
Figure 17.20 SCLi Timing
2
0
C
1
9
8 /
0 .
B
0
1
4
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"
(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)
0
SCLi
SDAi
SCLi
SDAi
SCLi
SDAi
SCLi
SDAi
(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"
G
3
J
6
u
i=0 to 4
IICM2 : Bit in the UiSMR2 register
CKPH : Bit in the UiSMR3 regiser
The above timing applies to the following setting :
• The CKDIR bit in the UiMR register is set to "1" (slave)
o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
1st
1st
1st
bit
bit
bit
1st
3
bit
0
D
D
D
2
D
5
7
7
7
C
7
8 /
2nd
2nd
2nd
Page 220
bit
2nd
bit
bit
bit
, 4
D
D
D
D
6
6
6
6
M
3
3rd
3rd
3rd
bit
3rd
bit
bit
bit
2
D
D
D
D
C
5
5
5
5
8 /
f o
4
4th
4th
4th
bit
bit
bit
4
4th
Data is transferred to the UiRB register
bit
) T
D
D
D
9
Data is transferred to the UiRB register
D
5
4
4
4
b15
4
•••
5th
5th
5th
bit
bit
bit
5th
bit
D
D
D
b9
D
Contents of the UiRB register
3
3
3
3
D
b8
0
6th
6th
6th
bit
bit
bit
6th
b7
bit
D
D
D
D
D
Data is transferred to the UiRB register
2
Data is transferred to the UiRB register
2
2
2
7
Receive interrupt
(DMA request)
D
Receive interrupt
(DMA request)
6
7th
bit
7th
7th
bit
bit
7th
bit
D
D
D
D
D
5
1
1
1
D
1
4
D
8th
8th
8th
bit
bit
bit
8th
3
bit
ACK interrupt (DMA
request) or NACK interrupt
ACK interrupt (DMA
request) or NACK interrupt
D
D
D
D
D
0
2
0
0
0
D
b0
1
9th
bit
9th
9th
9th
bit
bit
D
bit
D
D
D
8
8
8
Transmit interrupt
b15
b15
Data is transferred to the UiRB register
8
(ACK or NACK)
(ACK or NACK)
(ACK or NACK)
(ACK or NACK)
Transmit interrupt
•••
•••
b9
b9
Contents of the UiRB register
Contents of the UiRB register
D
D
b8
b8
8
0
D
b7
b7
7
D
D
6
7
b15
b15
D
D
17. Serial I/O (Special Function)
5
6
D
•••
•••
D
4
5
b9
Contents of the UiRB register
Contents of the UiRB register
D
b9
D
3
4
D
D
D
b8
b8
D
8
8
2
3
D
D
D
b7
D
b7
7
7
1
2
D
D
D
D
b0
b0
6
6
0
1
D
D
5
5
D
D
4
4
D
D
3
3
D
D
2
2
D
D
1
1
D
D
b0
b0
0
0