M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 341

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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2
NOTES:
NOTES:
n
NOTES:
Table 22.25 HDLC Processing Mode Specifications (Continued)
Table 22.26 Clock Settings (Communication Unit 0)
Table 22.27 Clock Settings (Communication Unit 1)
9 0
C
Transfer Clock
Transfer Clock
: Setting value of the G1PO0 register, 0001
. 1
Interrupt Request
1. See Figure 11.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit.
1. The transfer clock for reception is generated when the RSHTE bit in the G0ERC register is set to "1"
2. The CNT3 to CNT0 bits in the TCSPR register select no division (
1. The transfer clock for reception is generated when the RSHTE bit in the G1ERC register is set to "1"
2. The transfer clock is generated in single-phase waveform output mode of the channel 1.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (
8 /
B
1 0
0
4
(receive shift operation enabled).
(receive shift operation enabled).
3 0
G
J
2x(
- 6
. l u
o r
f
f
f
2n (2)
2n (3)
1 0
f
f
BT1
1
8
n
f
f
u
0
1
8
+2)
p
, 7
1 0
Item
(
0 2
M
(1)
(1)
5 0
3
(2)
2
(1)
C
8 /
Page 318
, 4
CCS2 Bit
M
CCS0 Bit
3
0
1
1
0
2
During transmit data processing,
During received data processing,
C
1
1
0
CCS Register
f o
8 /
• One of the following conditions can be selected to set the GiTOR bit in the
• When data, which is already converted to HDLC data, is transferred from the
• When data is transferred from the GiRI register to the GiRB register (reception
• When received data is transferred from the receive buffer of the GiRI register to
• When the GiTB register is compared to the GiCMPj register (j=0 to 3), the
receive register of the GiTO register to the transmit buffer, the GiTOR bit is set
to "1"
completed), the GiRIR bit is set to "1" (See Figure 11.14).
the receive register, the GiRIR bit is set to "1".
SRTiR bit is set to "1".
CCS Register
4
_
_
4
interrupt request register to "1" (interrupt request) (see Figure 11.14).
) T
5 9
When the IRS bit in the GiMR register is set to "0" (no data in the GiTB
When the IRS bit is set to "1" (transmission completed) and data transfer from
register) and data is transferred from the GiTB register to the transmit regis-
the transmit register to the GiTO register is completed.
ter (transmit start).
CCS3 Bit
CCS1 Bit
0
0
1
1
16
0
1
1
to FFFD
16
Specification
22. Intelligent I/O (Communication Function)
n
n
=0) or divide-by-2
=0) or divide-by-2
n
n
(
(
n
n
=1 to 15).
=1 to 15).