M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 89

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
Figure 8.3 EWCR0 to EWCR3 Registers
0
C
8.2.4 Bus Timing
1
9
0 .
8 /
B
Bus cycle for the internal ROM and internal RAM is basically one BCLK cycle. When the PM12 bit in the
PM1 register is set to "1" (wait state), the bus cycles are two BCLK cycles.
Bus cycles for the SFR are basically two BCLK cycles.
Basic bus cycle for an external space is 2ø (1ø+1ø) to read and to write. Bus cycle is selected by the
EWCRi register (i=0 to 3) from 12 types of separate bus settings and 7 types of multiplexed bus settings.
If the EWCRi04 to EWCRi00 bits are set to "00011
Figure 8.3 shows the EWCRi register. Figures 8.4 to 8.8 show bus timing in an external space.
0
1
4
0
3
G
J
6
u
o r
0 -
. l
External Space Wait Control Register i
b7
u
NOTES:
0
1
p
, 7
0
b6
1
(
1. The number of bus cycles from "when bus access begins" to "when RD or WR signal becomes "L".
2. The number of bus cycles from "when RD or WR signal becomes "L" to "when it becomes "H".
3. The EWCR0 to EWCR3 registers in M32C/84T cannot be used.
2
M
0
b5
3
0
5
2
b4
C
8 /
b3
Page 66
, 4
b2
M
3
b1
2
C
b0
f o
8 /
4
EWCRi00
EWCRi01
EWCRi02
EWCRi03
EWCRi04
EWCRi06
4
Symbol
) T
9
(b5)
(b7)
Bit
5
Symbol
EWCR0 to EWCR3
Bus Cycle Select Bit
Nothing is assigned.
When read, its content is indeterminate.
Recovery Cycle Addition
Select Bit
Nothing is assigned.
When read, its content is indeterminate.
Bit Name
Address
0048
2
" (1ø+3ø), bus cycles are four BCLK cycles.
16
, 0049
(i=0 to 3)
0 0 0 0 1: 1 + 1
0 0 0 1 0: 1 + 2
0 0 0 1 1: 1 + 3
0 0 1 0 0: 1 + 4
0 0 1 0 1: 1 + 5
0 0 1 1 0: 1 + 6
0 1 0 1 0: 2 + 2
0 1 0 1 1: 2 + 3
0 1 1 0 0: 2 + 4
0 1 1 0 1: 2 + 5
1 0 0 1 1: 3 + 3
1 0 1 0 0: 3 + 4
1 0 1 0 1: 3 + 5
1 0 1 1 0: 3 + 6
Do not set values other than the above
0 : Adds no recovery cycle when
1 : Adds a recovery cycle when
b4 b3 b2 b1 b0 (1)
16
, 004A
accessing external space i
accessing external space i
(3)
16
, 004B
Function
16
(2)
After Reset
X0X0 0011
2
RW
RW
RW
RW
RW
RW
RW
8. Bus