M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 275

• Manufacturer Part Number: M30845FJGP#U3
• Description: IC M32C MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30845FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
3
. v
J
2
Figure 18.5 AD0CON3 Register
0
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
o r
0 -
. l
A/D0 Control Register 3
b7
0 0 0
u
NOTES:
0
1
p
, 7
0
1. When the AD0CON3 register is rewritten during the A/D conversion, the conversion result is
2. The AD0CON3 may be read uncorrectly during the A/D conversion. It must be read or written after the
3. When the MSS bit is set to "1", set the DUS bit to "1".
4. When the DUS bit is set to "1", the AD00 register stores all A/D conversion results.
5. When the DUS bit is set to "1", set the DMAC.
6. When the MSS bit is set to "1", set the MD2 bit in the AD0CON1 register to "0" (other than repeat
7. Refer to the note for the CKS0 bit in the AD0CON0 register.
8. The MSF1 and MSF0 bit settings are enabled when the MSS bit is set to "1". Value in the bit is
b6
1
(
2
M
indeterminate.
A/D converter stops operating.
sweep mode 1), the APS1 and APS0 bits in the AD0CON2 register to "01
OPA1 and OPA0 bits in the AD0CON1 register to "00
indeterminate when the MSS bit is set to "0".
0
b5
3
0
5
2
b4
C
8 /
Page 252
b3
, 4
b2
M
3
b1
2
C
b0
f o
8 /
4
(b7 - b5)
4
Symbol
) T
CKS2
MSF0
MSF1
9
MSS
DUS
Bit
5
Symbol
AD0CON3
(1, 2)
Frequency Select Bit
DMAC Operation
Select Bit
Multi-Port Sweep
Mode Select Bit
Multi-Port Sweep
Status Flag
Reserved Bit
Bit Name
(3)
Address
0395
(8)
16
2
" (ANEX0 and ANEX1 not used).
Set to "0".
When read, its content is indeterminate.
(Note 7)
b4 b3
0 : Disables DMAC operating mode
1 : Enables DMAC operating mode
0 : Disables multi-port sweep mode
1 : Enables multi-port sweep mode
0 0 : AN
0 1 : AN15
1 0 : AN0
1 1 : AN2
0
0
0
to AN
0
to AN0
to AN2
to AN15
7
After Reset
XXXX X000
2
Function
7
7
" (AN15
7
0
2
to AN15
(3, 6)
(4, 5)
7
) and the
18. A/D Converter
RW
RW
RW
RW
RW
RO
RO