M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 99

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Figure 8.12 Bus Priority Order
Table 8.7 Microcomputer Status in Hold State
Table 8.8 External Bus States when Accessing Internal Space
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8.2.7 HOLD Signal
8.2.8 External Bus Status when Accessing Internal Space
8.2.9 BCLK Output
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The HOLD signal transfers bus privileges from the CPU to external circuits. When a low-level ("L") signal is
applied to the HOLD pin, the microcomputer enters a hold state after bus access is completed. While the
__________
HOLD pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal.
Table 8.7 shows the microcomputer status in a hold state.
Bus is used in the following priority order: HOLD, DMAC, CPU.
D
E
Table 8.8 shows external bus states when an internal space is accessed.
d
The CPU clock operates the CPU. P5
PM0 register is set to "0" (BCLK) and the CM01 and CM00 bits in the CM0 register are set to "00
port P5
No BCLK is output in single-chip mode. Refer to 9. Clock Generation Circuit for details.
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