M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 173

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
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14.2 DMAC II Performance
14.3 Transfer Data
e
E
3
. v
J
2
0
• Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space
• Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space.
• Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired
C
14.1.3 Interrupt Control Register for the Peripheral Function
14.1.4 Relocatable Vector Table for the Peripheral Function
14.1.5 IRLT Bit in the IIOiIE Register (i=0 to 4, 8 to 11)
Function to activate DMAC II is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II is
activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "111
peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral
function interrupt cannot be used.
When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "111
activated regardless of what state the I flag and IPL are in.
DMAC II transfers 8-bit or 16-bit data.
When a 16-bit data is transferred to the destination address 0FFFF
10000
depending on the internal RAM capacity.
14.3.1 Memory-to-memory Transfer
1
9
0 .
8 /
B
For the peripheral function interrupt activating DMAC II, set the ILVL2 to ILVL0 bits to "111
Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt
activating DMAC II.
When using the chained transfer, the relocatable vector table must be located in the RAM.
When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE
register of the interrupt to "0".
Data transfer between any two memory locations can be:
• a transfer from a fixed address to another fixed address
• a transfer from a fixed address to a relocatable address
• a transfer from a relocatable address to a fixed address
• a transfer from a relocatable address to another relocatable address
When a relocatable address is selected, the address is incremented, after a transfer, for the next transfer.
In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer address is
incremented by two.
When a source or destination address exceeds address 0FFFF
the source or destination address returns to address 00000
source and destination address at address 0FFFF
0
1
(Addresses 00000
memory location in a 64-Kbyte space.
4
0
3
G
J
16
6
u
o r
0 -
. l
. The same transfer occurs when the source address is 0FFFF
u
0
1
, 7
0
p
1
(
2
M
0
0
3
5
2
C
8 /
Page 150
, 4
16
M
to 0FFFF
3
2
C
f o
8 /
4
4
) T
9
16
5
) to another desired memory location in the same space.
16
or below.
16
and continues incrementation. Maintain
16
as a result of address incrementation,
16
16
, it is transferred to 0FFFF
. Actual transferable space varies
2
" (level 7), DMAC II is
2
" (level 7). These
2
" (level 7).
14. DMACII
16
and