M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 210

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
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3
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2
Figure 16.4 IDB0 and IDB1 registers, DTT Register
0
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
o r
0 -
. l
b7
Dead Time Timer
Three-Phase Output Buffer Register i
b7
NOTES:
u
0
1
NOTES:
p
, 7
0
1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a
b6
1
1. Use the MOV instruction to set the DTT register.
2. The DTT register setting is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time
(
2
transfer trigger.
signal level first. Then the value written in the IDB1 register on the falling edge of the timers A1, A2
and A4 one-shot pulse determines each phase output signal level.
M
After the transfer trigger occurs, the values written in the IDB0 register determine each phase output
0
enabled). No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06
bit in the INVC0 register determines start trigger of the DTT register.
b5
3
0
2
5
b4
C
8 /
Page 187
b3
, 4
b2
M
3
b1
2
C
b0
b0
f o
8 /
(1, 2)
4
(b7 - b6)
If setting value is n, the timer stops when counting
n times a count source selected by the INV12 bit
after start trigger occurs. Positive or negative
phase, which changes from inactive level to active
level, shifts when the dead time timer stops.
4
Symbol
) T
DWBi
DUBi
9
DVBi
DWi
DUi
DVi
5
Bit
Symbol
DTT
Symbol
IDB0, IDB1
U-Phase Output Buffer i
U-Phase Output Buffer i
V-Phase Output Buffer i
V-Phase Output Buffer i
W-Phase Output Buffer i
W-Phase Output Buffer i
Reserved Bit
Bit Name
Function
Address
030C
Address
030A
16
16
(1) (i=0, 1)
, 030B
16. Three-Phase Motor Control Timer Functions
16
Write output level
0: Active level
1: Inactive level
When read, the value of the three-
phase shift register is read.
When read,
its content is indeterminate
Function
After Reset
XX11 1111
Setting Range
After Reset
Indeterminate
1 to 255
2
RW
RW
RW
RW
RW
RW
RW
RO
RW
WO