M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 167

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
13.2 DMAC Transfer Cycle
13.3 Channel Priority and DMA Transfer Timing
3
. v
J
2
i= 0 to 3, p = 0 to 1
j, k=2 to 9
Table 13.3 DMAC Transfer Cycles
Table 13.4 Coefficient j, k
0
C
1
The number of DMAC transfer cycle can be calculated as follows.
Any combination of even or odd transfer read and write addresses are possible. Table 13.3 lists the number
of DMAC transfer cycles. Table 13.4 lists coefficient j, k.
Transfer Unit
8-bit transfers
(BWi bit in the DMDp
16-bit transfers
(BWi bit = 1)
When multiple DMA requests are generated in the same sampling period, between the falling edge of the
CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested)
simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3.
Figure 13.7 shows an example of the DMA transfer by external source.
In Figure 13.7, the DMA0 request having highest priority is received first to start a transfer when a DMA0
request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts.
After one DMA1 transfer is completed, the privilege is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when
DMA requests, as DMA1 in Figure 13.7, occur more than once before receiving bus privilege, the DRQ bit
is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is
completed.
9
Internal ROM
or internal RAM
with no wait state with a wait state
register = 0)
0 .
8 /
B
j=1
k=1
Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k
0
1
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
Internal Space
3
0
5
2
C
Internal ROM
or internal RAM area
8 /
Page 144
j=2
k=2
, 4
Bus Width Access Address
M
16-bit
16-bit
8-bit
8-bit
3
2
C
f o
8 /
4
4
) T
9
5
SFR
j=2
k=2
Even
Even
Even
Even
Odd
Odd
Odd
Odd
j and k BCLK cycles shown in Table 8.5.
Add one cycle to j or k cycles when inserting a recovery cycle.
Cycle
Read
Single-Chip Mode
1
1
1
2
External Space
Cycle
Write
1
1
1
2
Memory Expansion Mode
Microprocessor Mode
Cycle
Read
1
1
1
1
1
2
2
2
Cycle
Write
1
1
1
1
1
2
2
2
13. DMAC