M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 239

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
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17.3 Special Mode 1 (I
3
. v
J
2
Table 17.12 I
0
C
I
tions of I
a block diagram of I
Tables 17.15 to 17.17 list pin settings.
As shown in Table 17.12, I
"010
the SCLi pin level becomes low ("L") and stabilizes due to a SDAi transmit output via the delay circuit.
Interrupt
1
9
Selectable Function
2
8 /
0 .
B
C mode is a mode to communicate with external devices with a simplified I
0
1
4
0
2
G
3
J
" and the IICM bit in the UiSMR register is set to "1". Output signal from the SDAi pin changes after
6
u
o r
0 -
Item
. l
2
u
0
1
C mode. Table 17.13 lists register settings, Table 17.14 lists each function. Figure 17.19 shows
p
, 7
0
1
(
2
M
2
0
C Mode Specifications
3
0
2
5
C
8 /
Page 216
2
, 4
C mode. Figure 17.20 shows timings for transfer to the UiRB register and interrupts.
Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment
detect
M
• Arbitration lost
• SDAi digital delay
• Clock phase setting
3
2
The update timing of the ABT bit in the UiRB register can be selected.
Refer to 17.3.3 Arbitration
Selected from no digital delay or 2 to 8 cycle delay of the count source of the UiBRG register.
Refer to 17.3.5 SDA Output
Selected from clock delay or no clock delay.
Refer to 17.3.4 Transfer clock
2
C Mode)
2
C
C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to
8 /
f o
4
4
) T
9
5
Specifications
2
17. Serial I/O (Special Function)
C. Table 17.12 lists specifica-