M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 79

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
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7.2 Setting of Processor Mode
e
E
3
. v
J
2
Table 7.2 Processor Mode after Hardware Reset
Table 7.3 Processor Mode Selected by the PM01 and PM00 bit Settings
0
C
n I
N
V
V
The CNV
mode is selected. Table 7.2 lists processor mode after hardware reset. Table 7.3 lists processor mode
selected by PM01 and PM00 bit settings.
If the PM01 and PM00 bits are rewritten, the mode corresponding to the PM01 and PM00 bits is selected
regardless of CNV
Do not change the PM01 and PM00 bits to "01
mode) when the PM07 to PM02 bits in the PM0 register are being rewritten.
Do not enter microprocessor mode while the CPU is executing a program in the internal ROM.
Do not enter single-chip mode or memory expansion mode from microprocessor mode while the CPU is
executing a program in an external memory space, the same address assigned for the internal ROM.
The internal ROM cannot be accessed, regardless of PM01 and PM00 bit settings, when applying V
the CNVSS pin and generating the hardware reset (hardware reset 1 or low voltage detection reset).
Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in each
processor mode.
1
9
S
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O
0 .
8 /
p
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. 1
. 2
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4
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1
d
1
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(
pin state and the PM01 and PM00 bit settings in the PM0 register determine which processor
x
0
1
0
1
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Page 56
V
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p
p
7. Processor Mode
y l
n i
g
CC1
to