M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 396
Manufacturer Part Number
IC M32C MCU FLASH 512K 144LQFP
Renesas Electronics America
Specifications of M30845FJGP#U3
CAN, I²C, IEBus, SIO, UART/USART
DMA, PWM, WDT
Number Of I /o
Program Memory Size
512KB (512K x 8)
Program Memory Type
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
A/D 34x10b, D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Renesas Electronics America
24.5 Function Select Register C (PSC, PSC2, PSC3 Registers)
24.6 Function Select Register D (PSD1 Register)
24.7 Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers)
24.8 Port Control Register (PCR Register)
24.9 Input Function Select Register (IPS and IPSA Registers)
24.10 Analog Input and Other Peripheral Function Input
Figures 24.13 and 24.14 show the PSC, PSC2 and PSC3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSC register, the PSC2 register and
the PSC3 register select which peripheral function output is used.
Refer to 24.10 Analog Input and Other Peripheral Function Input for the PSC_7 bit in the PSC register.
Figure 24.14 shows the PSD1 register.
When multiple peripheral function outputs are assigned to a pin, the PSD1 register selects which peripheral
function output is used.
Figures 24.15 and 24.16 show the PUR0 to PUR4 registers.
The PUR0 to PUR4 registers select whether the ports, divided into groups of four ports, are pulled up or not.
Ports with bits in the PUR0 to PUR4 registers set to "1" (pull-up) and the direction registers set to "0" (input
mode) are pulled up.
Set bits in the PUR0 and PUR1 registers in P0 to P5, running as bus, to "0" (no pull-up) in memory expan-
sion mode and microprocessor mode. P0, P1 and P4
ports in memory expansion mode and microprocessor mode.
Figure 24.17 shows the PCR register.
The PCR register selects either CMOS output or N-channel open drain output as the P1 output format. If
the PCR0 bit is set to "1", N-channel open drain output is selected because the P-channel in the CMOS port
is turned off. This is, however, not a perfect open drain. Therefore, the absolute maximum rating of the
input voltage is between -0.3V and V
If P1 is used as the data bus in memory expansion mode and microprocessor mode, set the PCR0 bit to "0".
If P1 is used as a port in memory expansion mode and microprocessor mode, the PCR0 bit determines the
Figures 24.17 and 24.18 show the IPS and IPSA registers.
The IPS3, IPS1 and IPS0 bits in the IPS register and the IPSA_0 bit in the IPSA register select which pin is
assigned for the intelligent I/O or CAN input functions.
Refer to 24.10 Analog Input and Other Peripheral Function Input for the IPS2 bit.
The PSL3_6 to PSL3_3 bits in the PSL3 register, the PSC_7 bit in the PSC register and the IPS2 bit in the
IPS register each separate analog I/O ports from other peripheral functions. Setting the corresponding bit to
"1" (analog I/O) to use the analog I/O port (DA0, DA1, ANEX0, ANEX1, AN
prevents an intermediate potential from being impressed to other peripheral functions. The impressed inter-
mediate potential may cause increase in power consumption.
Set the corresponding bit to "0" (except analog I/O) when analog I/O is not used. All peripheral function
inputs except the analog I/O port are available when the corresponding bit is set to "0". These inputs are
indeterminate when the bit is set to "1". When the PSC_7 bit is set to "1", key input interrupt request remains
unchanged regardless of KI
pin input level change.
can be pulled up when they are used as input
24. Programmable I/O Ports