M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 390

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30845FJGP#U3M30845FJGP
Manufacturer:
TI
Quantity:
18 562
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
MIT
Quantity:
2 367
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
3
. v
J
2
Figure 23.39 Example of CAN Data Frame Receive Operation
Figure 23.38 Example of CAN Data Frame Transmit Operation
0
C
23.3.3 CAN Receive Timing
1
9
8 /
0 .
B
Figure 23.39 shows an operation example of when the CAN receives a frame.
0
1
4
0
G
3
(1) When the RECREQ bit in the C0MCTLj register (j= 0 to 15) is set to "1" (receive requested), the
(2) When the CAN starts receiving the frame, the RECSTATE bit in the C0STR register is set to "1"
(3) After the CAN frame reception is completed, the INVALDATA bit in the C0MCTLj register is set to
(4) After data is written to the message slot, the INVALDATA bit is set to "0" (storing receiving data)
J
6
u
o r
0 -
. l
NEWDATA bit
INVALDATA bit
RECSUCC bit
CAN bus
RECREQ bit
MBOX3 to
MBOX0 bits
RECSTATE bit
SISj bit
j=0 to 15
CAN is ready to receive the frame at anytime.
(during reception).
"1" (storing received data), the NEWDATA bit in the C0MCTLj register is set to "1" (receive com-
plete) and the RECSUCC bit in the C0STR register is set to "1" (reception completed).
and the SISj bit in the C0SISTR register is set to "1" (interrupt requested). The MBOX3 to MBOX0
bits in the C0STR register store received message slot numbers.
CAN bus
TRMSUCC bit
TRMREQ bit
MBOX3 to
MBOX0 bits
TRMSTATE bit
SISj bit
j=0 to 15
u
SENTDATA bit
TRMACTIVE bit
0
1
p
, 7
0
1
(
2
M
0
3
0
2
5
C
8 /
Page 367
, 4
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
M
Bus idle
3
Bus idle
2
C
(1)
Start transmtting
8 /
f o
4
4
Set to "1" by program
) T
Start receiving
9
(1)
5
(2)
Set to "1" by program
Receive frame
Transmit frame
Receive frame
Transmit frame
Reception completed
Transmission completed
(3)
(2)
(4)
Transmission-completed
message slot number
Reception-completed
message slot number
Intermission field
Intermission field
Bus idle
Bus idle
23. CAN Module