M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 175

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
14.6 Chained Transfer
14.7 End-of-Transfer Interrupt
e
E
3
. v
J
2
Figure 14.4 Relocatable Vector and DMAC II Index
0
(1) Transfer, caused by a transfer request source, occurs according to the content of the DMAC II index.
(2) When COUNT reaches "0", the contents of CADR1 and CADR0 are written to the vector of the request
(3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the
C
The CHAIN bit in MOD selects the chained transfer.
The following process initiates the chained transfer.
Figure 14.4 shows the relocatable vector and DMACII index when the chained transfer is in progress.
For the chained transfer, the relocatable vector table must be located in the RAM.
The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer
interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt is generated when COUNT reaches "0."
1
9
0 .
8 /
B
0
1
The vectors of the request source indicates where the DMAC II index is allocated. For each request, the
BRST bit selects either single or burst transfer.
source. When the INTE bit in MOD is set to "1", the end-of-transfer interrupt is generated simulta-
neously.
DMAC II index indicated by the peripheral function interrupt vector rewritten in (2).
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
, 7
0
p
1
(
2
M
0
0
3
Relocatable Vector
5
2
C
DMAC II
Index(2)
8 /
DMAC II
Index(1)
Page 152
, 4
M
3
2
C
f o
8 /
4
4
INTB
BASE(1)
(CADR1 to
BASE(2)
(CADR1 to
) T
CADR0)
CADR0)
9
5
BASE(2)
BASE(3)
RAM
Peripheral I/O interrupt vector causing DMAC II request
Default value of DMAC II is BASE(1).
The above vector is rewritten to BASE(2)
when a transfer is completed.
Starts at BASE(2) when next request conditions
are met.
Transferred according to the DMAC II Index.
The above vector is rewritten to BASE(3)
when a transfer is completed.
14. DMACII