M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 393

• Manufacturer Part Number: M30845FJGP#U3
• Description: IC M32C MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30845FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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When the CAN0 transmit interrupt request signal changes "0" to "1", the CAN01R bit in the IIO10IR
register is set to "1" (interrupt requested). If the CAN01E in the IIO10IE register is set to "1" (interrupt
enabled), the IR bit in the CAN1IC register is set to "1" (interrupt requested).
When the CAN0 error interrupt request signal changes "0" to "1", the CAN02R bit in the IIO11IR
register is set to "1" (interrupt requested). If the CAN02E in the IIO11IE register is set to "1" (interrupt
enabled), the IR bit in the CAN2IC register is set to "1" (interrupt requested).
The CAN0 error interrupt request signal remains set to "1" if another interrupt request causes the
corresponding bit in the C0EIMKR register is set to "1" and the corresponding bit in the C0EISTR to be
set to "1" after the CAN0 error interrupt request signal changes "0" to "1". The CAN02R and IR bits
also remain unchanged.
Bits in the C0SISTR or C0EISTR register and CAN0jR bits ( j=0 to 2) in the IIO9IR to IIO11IR registers
are not set to "0" automatically, interrupt acknowledgment notwithstanding. Set these bits to "0" by
program.
The CAN0 receive interrupt and CAN0 transmit interrupt are acknowledged when the CAN00R bit in
the IIO9IR register and the CAN01R bit in the IIO10IR register are set to "0". Corresponding bits in the
C0SISTR register can be set to either "0" or "1".
The CAN0 error interrupt is acknowledged when the CAN02R bit in the IIO11IR register and corre-
sponding bits in the C0EISTR register are set to "0".
If these bits remain set to "1", all CAN-associated interrupt request source become invalid.
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23. CAN Module