M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 217

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
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E
3
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2
Figure 17.1 UARTi Block Diagram
0
C
1
9
0 .
8 /
B
RxDi
0
1
4
0
CTSi / RTSi
3
G
J
6
u
o r
0 -
. l
RxDi
Selecting Clock Source
CLKi
u
0
1
SP
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in the UiMR register
CLK1 and CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register
UiERE: Bit in the UiC1 register
i=0 to 4
p
f
f
f
, 7
0
SP
2n
1
8
1
(2)
(
2
M
Inverse Circuit
10
01
00
0
STPS
2SP
CLK1 and
CLK0
RxD Data
1SP
1
1
Switching
0
CKPOL
3
Polarity
0
SP
Circuit
CLK
2
5
C
Switching Circuit
0
STPS
1SP
1
RxD Polarity
2SP
0
SP
8 /
Page 194
CRS 0
1
, 4
0
CTS/RTS
selected
CKDIR
Internal
External
0
PAR
M
Clock Synchronous
(when internal clock is selected)
0
1
PAR
Inverse
V
IOPOL
No inverse
3
1
SS
0
0
1
2
PRYE
PAR
enabled
PAR
disabled
1
0
C
CRD
PRYE
PAR
enabled
PAR
disabled
0
1
1 / (m+1)
0
Register
CTS/RTS disabled
f o
8 /
UiBRG
0
CTS/RTS disabled
4
4
Clock
Synchronous
) T
Clock
Asynchronous
9
SMD2 to SMD0
Clock
Asynchronous
SMD2 to SMD0
Clock
Synchronous
5
CRD
1
0
0
1/16
1/16
1/2
Clock Asynchronous
Clock Synchronous
(when external clock is
Clock Synchronous
selected)
Clock Synchronous
Clock Synchronous (when
internal clock is selected)
Clock Asynchronous
Receive
010, 100, 101, 110
010, 100, 101, 110
9-bit Clock
Asynchronous
9-bit Clock
Asynchronous
Type
0
7-bit Clock
Asynchronous
8-bit Clock
Asynchronous
Clock
Synchronous
CTSi
7-bit Clock
Asynchronous
8-bit Clock
Asynchronous
Clock
Synchronous
0
0
1
1
D
D
Transmit
8
RTSi
8
m : setting value of UiBRG register
NOTES:
001
001
1. P7
2. The CNT3 to CNT0 bits in the TCSPR register select no division
Clock
Synchronous
Clock
Synchronous
8-bit Clock
Asynchronous
9-bit Clock
Asynchronous
8-bit Clock
Asynchronous
9-bit Clock
Asynchronous
0
1
SMD2 to SMD0
not for the CMOS output.
(n=0) or divide-by-2n (n=1 to 15).
CKDIR
0
7-bit Clock
Asynchronous
and P7
0
0
1
1
D
D
7-bit Clock
Asynchronous
7
7
UiERE
Logic Inverse Circuit + MSB/LSB Conversion Circuit
Logic Inverse Circuit + MSB/LSB Conversion Circuit
High-order bits of data bus
Low-order bits of data bus
1
Control Circuit
Control Circuit
Error Signal Output
disable
Error Signal Output
enable
are ports for the N-channel open drain output, but
D
D
Transmit
6
6
Receive
1
0
D
D
Output Circuit
Error Signal
5
5
D
D
4
4
Receive
Clock
UARTi Transmit Register
Transmit
Clock
UARTi Receive Register
D
D
IOPOL
3
3
Inverse
0
1
D
D
Transmit/
2
2
No inverse
Receive
Inverse Circuit
Unit
TxD Data
D
D
1
1
D
D
0
0
Switching
Polarity
(Note 1)
Circuit
TxD
UiRB Register
UiTB Register
TxDi
17. Serial I/O
TxDi