M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 237

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
Figure 17.16 Transfer Format
Figure 17.17 Serial Data Logic Inverse
0
C
17.2.2 Selecting LSB First or MSB First
17.2.3 Serial Data Logic Inverse
1
9
0 .
8 /
B
As shown in Figure 17.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format.
This function is available for 8-bit transfer data.
When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB
register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB
register. Figure 17.17 shows a switching example of the serial data logic.
0
1
4
0
3
G
J
(1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first)
6
u
o r
0 -
. l
u
0
1
NOTES:
Transfer Clock
Transfer Clock
p
(2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first)
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
, 7
0
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (no inverse)
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
1
(
2
M
(no inverse)
transmitted on the falling edge of the transfer clock and received on the rising edge)
and the UiLCH bit in the UiC1 register is set to "0" (no inverse).
0
NOTES:
3
0
(inverse)
2
5
1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first),
C
TxD
TxD
8 /
the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE bit is set to "1"
(parity enabled).
Page 214
, 4
i
i
CLKi
RxD
CLKi
RxD
TxD
TxD
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
M
3
i
i
i
i
2
C
f o
8 /
4
4
) T
ST
ST
9
5
ST
ST
ST
ST
D
D
0
0
D
D
D
D
0
0
7
7
D
D
1
1
D
D
D
D
1
1
6
6
D
D
2
2
D
D
D
D
2
2
5
5
D
D
3
3
D
D
D
D
3
3
4
4
D
D
4
4
D
D
D
D
4
4
3
3
D
D
5
5
D
D
D
D
5
5
2
2
D
D
6
6
D
D
D
D
6
6
1
1
D
D
7
7
D
D
D
D
7
7
0
0
P
P
P
P
P
P
SP
SP
ST : Start bit
P : Parity bit
SP : Stop bit
SP
SP
SP
SP
17. Serial I/O (UART)