M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 305

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
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22.1 Base Timer
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3
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2
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Table 22.2 Base Timer Specifications
Count Source (f
Counting Operation
Counter Start Condition
Counter Stop Condition
Base Timer Reset Condition
Value when the Base Timer is Reset
Interrupt Request
Read from Base Timer
Write to Base Timer
Selectable Function
C
The base timer is a free-running counter that counts an internally generated count source.
Table 22.2 lists specifications of the base timer. Figures 22.3 and 22.4 show registers associated with the
base timer. Figure 22.9 shows a block diagram of the base timer. Figure 22.10 shows an example of the
base timer in counter increment mode. Figure 22.11 shows an example of the base timer in counter incre-
ment/decrement mode. Figure 22.12 shows an example of two-phase pulse signal processing mode.
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Page 282
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The base timer increments the counter value
The base timer increments and decrements the counter value
Two-phase pulse signal processing
The BTS bit in the G1BCR1 register is set to "1" (base timer starts counting)
The BTS bit in the G1BCR1 register is set to "0" (base timer reset)
• The value of the base timer matches the value of the G1PO0 register
• An low-level ("L") signal is applied to the INT0 or INT1 pin
• Bit 15 or bit 9 in the base timer overflows
"0000
The BT1R bit in the IIO4IR register is set to "1" (interrupt requested) when bit
9, bit 14 or bit 15 in the base timer overflows (See Figure 11.14.)
• The G1BT register indicates the counter value while the base timer is running
• The G1BT register is indeterminate when the base timer is reset
When a value is written while the base timer is running, the timer counter
immediately starts counting from this value. No value can be written while
the base timer is reset
• Counter increment/decrement mode
• Two-phase pulse processing mode
1
The base timer starts counting when the BTS bit is set to "1". After
incrementing to "FFFF
"0000
timer is reset by matching with the G1PO0 register), the timer counter
decrements two counts after the base timer matches the G1PO0 register.
The base timer increments the counter value again when the timer counter
reaches "0000
Two-phase pulse signals from P7
are counted as well. (See Figure 22.12.)
The IPSA_0 bit in the IPSA register controls input pin selection.
(Refer to 24. Programmable I/O Ports)
divided by
n
n
: determined by the DIV4 to DIV0 bits in the G1BCR0 register
=0 to 31; however no division when
16
"
16
". If the RST1 bit in the G1BCR1 register is set to "1" (the base
2(n+1)
P8
(P7
P8
(P7
0
1
16.
6
7
)
)
" (See Figure 22.11.)
, two-phase pulse input divided by
The timer increments
counter on all edge
16
", the timer counter is then decremented back to
Specification
6
and P7
n
The timer decrements
counter on all edges
________
=31
7
pins or P8
22. Intelligent I/O (Base Timer)
_______
2(n+1)
0
and P8
1
pins