M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 421

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30845FJGP#U3M30845FJGP
Manufacturer:
TI
Quantity:
18 562
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
MIT
Quantity:
2 367
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
25.2 Functions to Prevent the Flash Memory from Rewriting
e
E
3
. v
J
2
0
C
25.1.1 Boot Mode
The flash memory has the ROM code protect function for parallel I/O mode and the ID code verify function
for standard I/O mode to prevent the flash memory from reading or rewriting.
25.2.1 ROM Code Protect Function
25.2.2 ID Code Verify Function
1
9
0 .
8 /
B
The microcomputer enters boot mode when a hardware reset is performed while a high-level ("H") signal
is applied to the CNV
the boot ROM area is executed.
In boot mode, the FMR05 bit in the FMR0 register selects access to either the boot ROM area or the user
ROM area.
In the factory setting, the rewrite control program for standard serial I/O mode is stored into the boot ROM
area.
The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erase-
write mode 0 (EW mode 0) is written in the boot ROM area, the flash memory can be rewritten according
to the system implemented.
The ROM code protect function prevents the flash memory from reading and rewriting in parallel I/O
mode.
Figure 25.2 shows the ROMCP register. The ROMCP register is located in the user ROM area.
The ROM code protect function is enabled when the ROMCP1 bit is set to "00
Use the ID code verify function in standard serial I/O mode. The ID code sent from the serial programmer
is compared with the ID code written in the flash memory for a match. If the ID codes do not match,
commands sent from the serial programmer are not accepted. However, if the four bytes of the reset
vector are "FFFFFFFF
The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses
0FFFFDF
memory must have a program with the ID codes set in these addresses.
0
1
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
1
16
(
2
M
, 0FFFFE3
0
3
0
2
5
C
8 /
Page 398
, 4
SS
M
16
16
3
and P5
, 0FFFFEB
2
", ID codes are not compared, allowing all commands to be accepted.
C
f o
8 /
4
4
) T
9
0
5
pins and a low-level ("L") signal is applied to the P5
16
, 0FFFFEF
16
, 0FFFFF3
16
, 0FFFFF7
16
and 0FFFFFB
2
", "01
25. Flash Memory Version
5
2
" or "10
pin. A program in
16
. The flash
2
".