M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 159

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Table 13.1 DMAC Specifications
0
Channels
Transfer Memory Space
Maximum Bytes Transferred
DMA Request Source
Channel Priority
Transfer Unit
Destination Address
Transfer Mode Single Transfer Transfer is completed when the DCTi register (i = 0 to 3) is set to "0000
DMA Interrupt Request Generation Timing When the DCTi register changes "0001
DMA Startup
DMA Stop
Reload Timing to the DCTi
or DMAi Register
DMA Transfer Cycles
NOTES:
C
1
DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt
request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a
DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. There-
fore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In
addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged.
9
0 .
8 /
B
1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.
0
1
4
0
3
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0
1
Item
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0
1
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0
3
0
Repeat Transfer When the DCTi register is set to "0000
Repeat Transfer DMA stops when the MDi1 and MDi0 bits are set to "00
Single Transfer DMA stops when the MDi1 and MDi0 bits are set to "00
5
2
Single Transfer DMA starts when a DMA request is generated after the DCTi register is
Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is
C
8 /
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(1)
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When the DCTi register is set to "0000
4 channels (cycle-steal method)
• From a desired address in a 16-Mbyte space to a fixed address in a
• From a fixed address in a 16-Mbyte space to a desired address in a
128 Kbytes (when a 16-bit data is transferred) or 64 Kbytes (with an 8-
bit data is transferred)
Falling edge or both edges of signals applied to the INT0 to INT3 pins
Timers A0 to A4 interrupt requests
Timers B0 to B5 interrupt requests
UART0 to UART4 transmit and receive interrupt requests
A/D0 conversion interrupt request
Intelligent I/O interrupt request
CAN interrupt request
Software trigger
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority)
8 bits, 16 bits
specifying source and destination addresses simultaneously)
is reloaded into the DCTi register and the DMA transfer is continued
set to "0001
(j = 0, 1) are set to "01
set to "0001
(repeat transfer)
abled) and the DCTi register is set to "0000
transfer or write
register is set to "0000
fer mode
Minimum 3 cycles between SFR and internal RAM
Forward/fixed (forward and fixed directions cannot be specified when
5
16-Mbyte space
16-Mbyte space
16
16
" or more and the MDi1 and MD0 bits in the DMDj register
" or more and the MDi1 and MD0 bits are set to "11
2
16
" (single transfer)
" and the DRCi register set to "0000
Specification
16
16
16
", the value of the DRCi register
" from "0001
" to "0000
16
" (0 DMA transfer) by DMA
16
________
16
"
" in repeat trans-
2
" and the DCTi
2
" (DMA dis-
________
16
"
13. DMAC
16
2
"
"