M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 298

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
0
C
Figure 22.2 Intelligent I/O Communication Block Diagram
1
9
8 /
0 .
B
0
1
4
NOTES:
0
ISRxD0
1. Each register enters after the G1BCR0 register supplies the clock.
2. See Figure 11.14.
G
Generated Clock in
the Channel i (i=1 to 3)
3
J
6
u
o r
ISCLK1
ISRxD1
0 -
. l
ISCLK0
u
0
1
p
, 7
0
1
(
f
2
M
G0RI Register
2n
0
Receive
Receive
Receive Operation Clock
Register
Buffer
3
0
f
f
f
1
2n
8
2
5
G1RI Register
0
1
C
Receive
Receive
Register
CKDIR
Buffer
CCS1 and CCS0
01
10
11
8 /
Page 275
00
01
10
11
CCS3 and CCS2
, 4
Operation
1
Transmit
Clock
RXSL
M
0
1
3
2
RXSL
0
0
1
C
CKDIR
8 /
f o
4
4
Polarity
Inverse
) T
9
Operation
Operation
Receive
5
Transmit
Clock
Clock
(Receive Data Register)
G0CMP0 register
(Transmit Buffer Register)
G0CMP0 register
G0DR Register
Arbitration
(Receive Data Register)
G1CMP0 Register
G0CMP0 register
G0TB Register
(Transmit Buffer Register)
Control Circuit
G1CMP0 Register
Clock Wait
Register
Register
G0CMP3 Register
Buffer
Transmit
Transmit
Shift
Arbitration
G1DR Register
Register
G1CMP0 Register
Buffer
(8bit)
G1TB Register
Control Circuit
G1CMP3 Register
Register
Register
Clock Wait
Buffer
(8bit)
Communication Unit 0
Communication Unit 1
Transmit
Shift
Transmit
Register
Buffer
(8bit)
G0RCRC
Generation Circuit
Register
Bit Insert Check
Bit Insert Circuit
Transmit Latch
G1RCRC
Generation Circuit
Generation Circuit
Generation Circuit
SOF
Register
Bit Insert Check
Bit Insert Circuit
Start Bit Check
Stop Bit Check
CKDIR : Bit in the GiMR Register (i=0,1)
TXSL, RXSL : Bits in the GiEMR Register
CCS1 and CCS0 : Bits in the CCS Register
Transmit Latch
Start Bit
Stop Bit
Comparator
SOF
Comparator
Generation Circuit
Comparator
Receive Data
Comparator
Comparator
Comparator
Selector
(8bit)
Data
Generation Circuit
Comparator
Selector
(8bit)
Data
Receive Data
Generation Circuit
Comparator
(8bit)
Transmit Data
Selector
Data
Selector
Data
Generation Circuit
G0TCRC
Register
Transmit Data
G1TCRC
Register
Special Interrupt
G0TO Register
G0RB Register
Check
TXSL
Transmit
Transmit
Receive
Special Interrupt
Receive
Register
Reception
Register
Transmission
Buffer
Buffer
Reception
G1TO Register
G1RB Register
Transmission
TXSL
1
Check
Transmit
Transmit
Receive
0
1
Receive
Register
Register
Buffer
Buffer
0
Polarity
Inverse
Transmit Interrupt Request
SIO0TR
Transmit Interrupt
Request
SIO1TR
HDLC Data Receive
Interrupt Request
G1RIR
HDLC Data Transmit
Interrupt Request
G0TOR
Special
Communication
Interrupt Request
SRT1R
HDLC Data
Transmit
Interrupt Request
G1TOR
Receive Interrupt
Request
Special
Communication
Interrupt Request
SRT0R
Receive Interrupt
Request
SIO0RR
HDLC Data Receive
Interrupt Request
G0RIR
(2)
22. Intelligent I/O
ISTxD0
ISTxD1
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)