M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 266

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
e
E
3
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J
2
Figure 17.29 SIM Interface Operation
0
C
1
9
0 .
8 /
B
0
1
(1) Transmit Timing
4
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
Parity Error Signal
returned from
Receiving End
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
Transfer Clock
RE bit in UiC1
register
Transmit Waveform
from the
Transmitting End
RI bit in UiC1
register
IR bit in SiRIC
register
TxDi
Signal Line Level
TxDi
Signal Line Level
0
(2) Receive Timing
3
G
J
6
u
NOTES:
o r
0 -
. l
u
0
1
i=0 to 4
The above applies to the following settings :
i=0 to 4
The above applies to the following settings :
1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit.
2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi
3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the
4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15).
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
, 7
0
p
pin and parity error signal from the receiving end, is generated.
transmitting end and parity error signal from the TxDi pin, is generated.
when transmission completed)
1
(
2
M
0
0
3
(2)
(3)
5
2
C
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
8 /
Page 243
, 4
M
3
Start
ST
ST
ST
ST
2
Start
bit
bit
C
D
D
f o
D
8 /
D
0
0
0
0
4
4
D
D
D
D
) T
9
1
1
1
1
5
Tc
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
D
D
5
5
5
5
D
D
D
D
Data is written to
the UARTi register
6
6
6
6
D
D
D
D
7
7
7
7
Parity
Parity
P
P
bit
bit
P
P
SP
SP
SP
SP
Stop
Stop
bit
bit
Set to "0" by an interrupt request acknowledgement or by program
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16(m+1) / f
Tc = 16(m+1) / f
f
m : setting value of the UiBRG register
f
m : setting value of the UiBRG register
j
j
: count source frequency of the UiBRG register (f
: count source frequency of the UiBRG register (f
ST
ST
ST
ST
An interrupt routine
detects "H" or "L"
Data is transferred from the UiTB
register to the UARi transmit register
(Note 1)
An "L" signal is applied from the SIM
card due to a parity error
D
D
D
D
0
0
0
0
Read the UiRB register
j
j
D
D
D
D
1
1
1
1
D
D
D
D
2
2
2
2
D
TxDi outputs "L" due to
a parity error
D
D
D
3
3
3
17. Serial I/O (Special Function)
3
D
D
D
D
4
4
4
4
An interrupt routine detects
"H" or "L"
D
D
D
D
5
5
5
5
D
D
D
D
6
6
6
6
D
D
D
D
7
7
7
7
P
P
P
P
1
SP
1
SP
, f
, f
8,
SP
8,
SP
f
2n (4)
f
2n (4)
)
)