M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 235

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
Figure 17.14 Transmit Operation
0
C
1
9
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
CTSi
TxDi
TXEPT bit in UiC0
register
IR bit in SiTIC
register
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
TxDi
TXEPT bit in UiC0
register
IR bit in SiTIC
register
0 .
8 /
(1) 8-bit Data Transmission Timing (with a parity and 1 stop bit)
(2) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
B
i=0 to 4
The above timing applies to the following settings :
0
1
4
i=0 to 4
The above timing applies to the following settings :
0
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The CRD bit in the UiC
• The UilRS bit in the UiC1 register is set to "1"
3
G
J
to "0" (CTS function selected)
(transmission completed)
• The PRYE bit in the UiMR register is set to "0" (parity disabled)
• The STPS bit in the UiMR register is set to "1" (2 stop bits)
• The CRD bit in the UiC0 register is set to "1" (CTS function
• The UilRS bit in the UiC1 register is set to "0" (no data in the
6
disabled)
transmit buffer)
u
o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
"1"
"0"
"1"
"0"
"H"
"L"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
3
0
2
5
C
8 /
Page 212
, 4
0
register is set to "0" and the CRS bit is set
Start
ST
M
Start
ST
bit
bit
3
D
Data is set in the UiTB register
2
D
0
Set to "0" by an interrupt request acknowledgement or by program
0
C
Data is set in the UiTB register
D
D
f o
8 /
1
1
4
D
4
Tc
D
2
) T
9
2
5
D
D
3
3
Tc
D
Data is transferred from the UiTB register to the UARTi transmit register
The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin,
when the stop bit is verified.
The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin.
D
4
4
D
D
Data is transferred from the UiTB register to the UARTi transmit register
5
5
D
D
6
6
D
Parity
D
7
bit
7
D
P
8
Stop
SP
bit
SP
SP
Tc = 16 (m + 1) / f
NOTES:
Tc = 16 (m + 1) / f
NOTES:
Set to "0" by an interrupt request acknowledgement or by program
Stop
bit
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0)
1. The CNT3 to CNT0 bits in the TCSPR register select no division
ST
Stop
or divide-by-2n (n=1 to 15).
f
f
clock)
m : setting value of the UiBRG register
(n=0) or divide-by-2n (n=1 to 15).
bit
j
EXT
f
f
clock)
m : setting value of the UiBRG register
j
EXT
: count source frequency set in the UiBRG register (f
: count source frequency set in the UiBRG register (f
ST
D
0
: count source frequency set in the UiBRG register (external
: count source frequency set in the UiBRG register (external
D
D
0
1
D
D
1
2
j
j
or 16 (m + 1) / f
or 16 (m + 1) / f
D
D
2
3
D
D
Pulse stops because the TE bit is set to "0"
3
4
D
D
4
5
D
D
5
6
EXT
EXT
D
D
6
7
D
P
7
D
SP
8
SP SP
17. Serial I/O (UART)
ST
1
1
ST
, f
D
, f
0
8
8
, f
, f
D
D
2n (1)
2n (1)
0
1
D
)
1
)