M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 302

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
0
Figure 22.6 G1TM0 to G1TM7 Registers and G1POCR0 to G1POCR7 Registers
C
1
9
8 /
0 .
B
0
1
4
0
G
3
J
6
u
o r
0 -
. l
u
0
1
b15
Time Measurement Register 1j (j=0 to 7)
Waveform Generating Control Register 1j (j=0 to 7)
b7
p
, 7
0
NOTES:
1
(
2
b6
M
1. This setting is enabled only for even channels. In SR waveform output mode, values written to the
2. To receive data in UART mode, set the G1POCR2 register to "0000 0110
3. This setting is enabled only for channels 0 and 1. To use the ISTxD1 pin, set the MOD2 to MOD0 bits
4. The BTRE bit is provided in the G1POCR0 register only. Set each bit 6 in the G1POCR1 to
5. The inverse output function is the final step in waveform generating process. When the INV bit is set
6. To provide either "H" or "L" signal output set in the IVL bit, set the FSCj bit in the G1FS register to "0"
7. When the BTRE bit is set to "1", set the BCK1 and BCK0 bits in the G1BCR0 register to "11
0
3
corresponding odd channel (next channel after an even channel) are ignored. Even channels provides
waveform output. Odd channels provides no waveform output.
in the G1POCR0 register to "111
in the G1POCR1 register to"111
and 1 and for the communication function.
G1POCR7 registers to "0".
to "1", an "H" signal is provided a default output by setting the IVL bit to "0"; and an "L" signal is
provided by setting it to "1".
(the time measurement function selected) and IFEj bit in the G1FE register to "1" (functions for
channel j enabled). Then set the IVL bit to "0" or "1".
the UD1 and UD0 bits in the G1BCR1 register to "00
0
b5
2
5
C
b4
b8
8 /
Page 279
b7
, 4
b3
M
b2
3
2
b1
C
8 /
b0
f o
b0
4
4
) T
Symbol
G1TM0 to G1TM2
G1TM3 to G1TM5
G1TM6, G1TM7
The base timer value is stored every
measurement timing
9
Symbol
MOD0
MOD1
MOD2
BTRE
5
RLD
(b3)
INV
IVL
Bit
Symbol
G1POCR0
G1POCR1 to G1POCR3
G1POCR4 to G1POCR7
2
2
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Output Initial Value
Select Bit
G1POj Register Value
Reload Timing Select Bit
Base Timer Reset Enable
Bit
Inverse Output Function
Select Bit
". Do not set the MOD2 to MOD0 bits to "111
Operating Mode
Select Bit
". To use the ISCLK1 pin for an output, set the MOD2 to MOD0 bits
(4)
Bit Name
0101
0107
010D
Address
Function
(6)
(5)
16
16
16
- 0100
- 0106
- 010C
Address
0110
0111
0114
2
16,
16,
" (counter increment mode).
16,
0103
0109
16
16
16
010F
, 0112
, 0115
b2
0
0
0
0
1
1
1
1
0: "L" output as default value
1: "H" output as default value
0: Reloads the G1POj register when
1: Reloads the G1POj register when
0: Disables base timer reset when
1: Enables base timer reset when
0: Output is not inversed
1: Output is inversed
b1
16
16
0
0
1
1
0
0
1
1
16
bit 15 in the base timer overflows
bit 9 in the base timer overflows
value is written
the base timer is reset
b0
0
1
0
1
0
1
0
1
- 0102
- 0108
16
16
- 010E
: Single waveform output mode
: SR waveform output mode
: Phase-delayed waveform
: Do not set to this value
: Do not set to this value
: Do not set to this value
: Do not set to this value
: Use communication function
output mode
output
, 0113
, 0116
16,
16,
16
16
16
(3)
0105
010B
, 0117
Function
2
".
16
16
Setting Range
16
2
- 0104
- 010A
" except in channels 0
16
16
After Reset
0000 X000
0X00 X000
0X00 X000
(2)
After Reset
Indeterminate
Indeterminate
Indeterminate
2
(1)
" (f
(7)
2
2
2
1
) and
22. Intelligent I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO