M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 337

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30845FJGP#U3M30845FJGP
Manufacturer:
TI
Quantity:
18 562
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
MIT
Quantity:
2 367
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R
R
M
e
E
3
. v
J
2
NOTES:
Table 22.20 UART Mode Specifications (Communication Unit 1)
9 0
C
22.4.2 Clock Asynchronous Serial I/O (UART) Mode (Communication Unit 1)
Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Error Detection
Selectable Function
. 1
1. The transfer clock must be f
2. When an overrun error occurs, the G1RB register is indeterminate.
8 /
B
In clock asynchronous serial I/O (UART) mode, data is transmitted at a desired bit rate and in a desired
transfer data format. Table 22.20 lists specifications of UART mode in the communication unit 1. Table
22.21 lists clock settings. Table 22.22 lists register settings. Tables 22.23 and 22.24 list pin settings.
Figure 22.30 shows an example of transmit operation. Figure 22.31 shows an example of receive opera-
tion.
1 0
0
4
3 0
G
J
- 6
. l u
o r
1 0
u
0
p
, 7
1 0
Item
(
0 2
M
(1)
5 0
3
2
C
8 /
Page 314
, 4
M
3
2
• Character Bit (transfer data) :
• Start bit :
• Parity bit:
• Stop bit :
See Table 22.21
Set registers associated with the waveform generating function, the G1MR register and
G1ERC register. Then, set as written below after at least one transfer clock cycle.
• Set the TE bit in the G1CR register to "1" (transmit enable)
• Set the TI bit in the G1CR register to "0" (data written to the G1TB register)
Set registers associated with the waveform generating function, the G1MR register and
G1ERC register. Then, set as written below after at least one transfer clock cycle.
• Set the RE bit in the G1CR register to "1" (receive enable)
• Detect the start bit
• While transmitting, one of the following conditions can be selected to set the
• While receiving, the following condition can be selected to set the SIO1RR bit is set
• Overrun error
• Parity error
• Framing error
• Stop bit length
• LSB first or MSB first
C
SIO1TR bit to "1" (interrupt requested) (See Figure 11.14.) :
next data is received before reading the G1RB register
This error occurs, when the next data reception is started and the final stop bit of the
f o
8 /
_
_
to "1":
Data is transferred from the receive register to the G1RB register (data reception
is completed)
While parity is enabled, this error occurs when the number of "1" in parity and char-
acter bits does not match the number of "1" set
This error occurs when the number of the stop bits set is not detected
The length of the stop bit is selected from 1 bit or 2 bits
Select either bit 0 or bit 7 to transmit or receive data
4
is transferred to the transmit register from the G1TB register.
transmit register is completed
The IRS bit in the G1MR register is set to "0" (no data in the G1TB register) and data
4
The IRS bit is set to "1" (transmission completed) and data transfer from the
BT1
) T
5 9
divided by six or more.
(2)
8 bits long
1 bit long
selected from odd, even, or none
selected length from 1 bit or 2 bits
Specification
22. Intelligent I/O (Communication Function)