M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 171

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
e
E
3
. v
J
2
Figure 14.2 DMAC II Index
0
C
14.1.2 DMAC II Index
1
9
0 .
8 /
B
transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter,
source address (or immediate data), operation address as an address to be calculated, destination ad-
dress, chained transfer address, and end-of-transfer interrupt address.
This DMAC II index must be located on the RAM area.
Figure 14.2 shows a configuration of the DMAC II index. Table 14.2 lists a configuration of the DMAC II
index in transfer mode.
The followings are details of the DMAC II index. Set these parameters in the specified order listed in
Table 14.2, according to DMAC II transfer mode.
The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple
0
1
• Transfer mode (MOD)
• Transfer counter (COUNT)
• Transfer source address (SADR)
• Operation address (OADR)
• Transfer destination address (DADR)
• Chained transfer address (CADR)
• End-of-transfer interrupt address (IADR)
4
0
DMAC II Index
Starting Address
(BASE)
3
G
J
6
the calculation transfer function.
this data only when using the chained transfer function.
data only when using the end-of-transfer interrupt.
u
Two-byte data is required to set transfer mode. Figure 14.3 shows a configuration for transfer mode.
Two-byte data is required to set the number of transfer.
Two-byte data is required to set the source memory address or immediate data.
Two-byte data is required to set a memory address to be calculated. Set this data only when using
Two-byte data is required to set the destination memory address.
Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set
Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this
The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation
transfer function, set destination address to BASE+6. (See Table 14.2)
Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request.
o r
0 -
. l
u
0
1
BASE + 2
BASE + 4
BASE + 6
BASE + 8
BASE + 10
BASE + 12
BASE + 14
BASE + 16
, 7
0
p
1
NOTES:
(
2
Memory-to-Memory Transfer, Immediate Transfer,
Calculation Transfer
M
0
1. This data is not required when not using the calculation transfer function.
2. This data is not required when not using the chained transfer function.
3. This data is not required when not using the end-of-transfer interrupt.
0
3
5
2
C
8 /
Transfer Counter
Transfer Source Address (or immediate data) (SADR)
Operation Address
Transfer Destination Address
Chained Transfer Address
Chained Transfer Address
End-of-Transfer Interrupt Address
End-of-Transfer Interrupt Address
Page 148
Transfer Mode
, 4
M
3
2
C
f o
8 /
4
4
(1)
) T
9
16 bits
5
(2)
(2)
(3)
(3)
(COUNT)
(OADR)
(DADR)
(CADR0)
(CADR1)
(IADR0)
(IADR1)
(MOD)
BASE
BASE + 2
BASE + 4
BASE + 6
BASE + 8
BASE + 10
BASE + 28
BASE + 30
Multiple Transfer
Transfer Counter
Transfer Source Address
Transfer Destination Address
Transfer Source Address
Transfer Destination Address
Transfer Source Address
Transfer Destination Address
Transfer Mode
16 bits
(COUNT)
(SADR1)
(DADR1)
(SADR2)
(DADR2)
(SADR7)
(DADR7)
(MOD)
14. DMACII