M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 174

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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14.4 Transfer Modes
14.5 Multiple Transfer
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14.3.2 Immediate Data Transfer
14.3.3 Calculation Transfer
Single and burst transfers are available. The BRST bit in MOD selects transfer method, either single trans-
fer or burst transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set
to "0000
14.4.1 Single Transfer
14.4.2 Burst Transfer
The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memory-to-
memory transfer. One transfer request source initiates multiple transfers. The CNT2 to CNT0 bits in MOD
selects the number of transfers from "001
"000
The transfer source and destination addresses for each transfer must be allocated alternately in addresses
following MOD and COUNT. When the multiple transfer is selected, the calculation transfer, burst transfer,
end-of-transfer interrupt and chained transfer cannot be used.
1
9
0 .
8 /
B
DMAC II transfers immediate data to any memory location. A fixed or relocatable address can be se-
lected as the destination address. Store the immediate data into SADR. To transfer an 8-bit immediate
data, write the data in the low-order byte of SADR (high-order byte is ignored).
After two memory data or an immediate data and memory data are added together, DMAC II transfers
calculated result to any memory location. SADR must have one memory location address to be calcu-
lated or immediate data and OADR must have the other memory location address to be calculated. Fixed
or relocatable address can be selected as source and destination addresses when using a memory +
memory calculation transfer. If the transfer source address is relocatable, the operation address also
becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address
when using an immediate data + memory calculation transfer.
For every transfer request source, DMAC II transfers one transfer unit of 8-bit or 16-bit data once. When
the source or destination address is relocatable, the address is incremented, after a transfer, for the next
transfer.
COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the inter-
rupt is acknowledged when COUNT reaches "0".
For every transfer request source, DMAC II continuously transfers data the number of times determined
by COUNT. COUNT is decremented every time a transfer occurs. The burst transfer ends when COUNT
reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer ends if using the end-
of-transfer interrupt. All interrupts are ignored while the burst transfer is in progress.
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Page 151
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" (once) to "111
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14. DMACII