M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 169

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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14. DMAC II
14.1 DMAC II Settings
e
E
3
. v
J
2
DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which
transfers the sum of two data added by an interrupt request from any peripheral functions.
Table 14.1 lists specifications of DMAC II.
Table 14.1 DMAC II Specifications
NOTES:
0
C
DMAC II Request Source
Transfer Data
Transfer Block
Transfer Space
Transfer Direction
Transfer Mode
Chained Transfer Function Parameters (transfer count, transfer address and other information) are
End-of-Transfer Interrupt
Multiple Transfer Function
DMAC II can be made available by setting up the following registers and tables.
• RLVL register
• DMAC II Index
• Interrupt control register of the peripheral function causing a DMAC II request
• The relocatable vector table of the peripheral function causing a DMAC II request
• IRLT bit in the IIOiIE register (i = 0 to 4, 8 to 11) if using the intelligent I/O or CAN interrupt
14.1.1 RLVL Register
1
9
Refer to 11. Interrupts for details on the IIOiIE register.
0 .
8 /
B
1. When transferring a 16-bit data to destination address 0FFFF
2. The actual space where transfer can occurs is limited due to internal RAM capacity.
When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), DMAC II is
activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the interrupt
control register set to "111
Figure 14.1 shows the RLVL register.
0
1
4
0
10000
3
G
J
6
u
o r
0 -
. l
u
0
1
, 7
0
p
16
1
Item
(
. The same transfer occurs when the source address is 0FFFF
2
M
0
0
3
5
2
C
8 /
Page 146
, 4
M
3
2
C
2
ILVL0 bits are set to "111
• Data in memory is transferred to memory (memory-to-memory transfer)
• Immediate data is transferred to memory (immediate data transfer)
• Data in memory (or immediate data) + data in memory are transferred to
memory (calculation transfer)
8 bits or 16 bits
64-Kbyte space in addresses 00000
switched when transfer counter reaches zero
Interrupt occurs when a transfer counter reaches zero
Multiple data can be transferred by a generated request for one DMAC II transfer
Fixed or forward address
Single transfer, burst transfer
Interrupt requests generated by all peripheral functions when the ILVL2 to
" (level 7).
f o
8 /
Selected separately for each source address and destination address
4
4
) T
9
5
2
"
Specification
16
to 0FFFF
16
, it is transferred to 0FFFF
16
16 (1, 2)
.
14. DMACII
16
and