M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 329

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
e
E
3
. v
J
2
Figure 22.26 G0IRF Register
9 0
C
. 1
8 /
B
1 0
0
4
3 0
G
J
- 6
. l u
o r
SI/O Special Communication Interrupt Detect Register 0
1 0
b7
u
NOTES:
0
p
, 7
1 0
b6
1. The G0IRF register is used in HDLC data processing mode. Do not use in clock synchronous serial
2. The SRT0R bit in the IIO4IR register is set to "1" if the BSERR or IRF0 to IRF3 bit is set to "1".
(
0 2
M
I/O mode.
b5
5 0
3
2
b4
C
8 /
Page 306
b3
0
, 4
b2
M
3
0 0
b1
2
C
b0
f o
8 /
(b1 - b0)
4
Symbol
BSERR
4
) T
IRF0
IRF1
IRF2
IRF3
5 9
(b3)
Bit
Symbol
G0IRF
Reserved Bit
Bit Stuffing Error
Detect Flag
Reserved Bit
Interrupt Cause
Determination
Flag 0
Interrupt Cause
Determination
Flag 1
Interrupt Cause
Determination
Flag 2
Interrupt Cause
Determination
Flag 3
Bit Name
Address
00FE
Set to "0"
0 : Not detected
1 : Detected
Set to "0"
0 : The G0DR register (receive data register)
1 : The G0DR register matches the G0CMP0
0 : The G0DR register (receive data register)
1 : The G0DR register matches the G0CMP1
0 : The G0DR register (receive data register)
1 : The G0DR register matches the G0CMP2
0 : The G0DR register (receive data register)
1 : The G0DR register matches the G0CMP3
does not match the G0CMP0 register
register
does not match the G0CMP1 register
register
does not match the G0CMP2 register
register
does not match the G0CMP3 register
register
16
22. Intelligent I/O (Communication Function)
Function
After Reset
00
16
(1, 2)
RW
RW
RW
RW
RW
RW
RW
RW