M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 342

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
i=0, 1
NOTES:
Table 22.28 Register Settings in HDLC Processing Mode (Communication Units 0 and 1)
0
C
G1BCR0
G1BCR1
G1POCR0
G1POCR1
G1PO0
G1PO1
G1FS
G1FE
GiMR
GiEMR
GiCR
GiETC
GiERC
GiIRF
GiCMP0,
GiCMP1
GiCMP2
GiCMP3
GiMSK0,
GiMSK1
GiTCRC
GiRCRC
GiTO
GiRI
GiRB
GiTB
CCS
1
9
1. These register settings are required when the CCS3 and CCS2 bit in the CCS register are set to "00
0 .
8 /
B
Register
0
1
4
(clock output from channel j (j=1,2,3)).
0
3
G
(1)
(1)
J
6
u
(1)
(1)
o r
0 -
. l
(1)
u
0
1
(1)
(1)
p
, 7
0
1
(
2
M
0
3
0
BCK1, BCK0
DIV4 to DIV0
IT
7 to 0
7 to 0
7 to 0
15 to 0
15 to 0
FSC1, FSC0
IFE1, IFE0
GMD1, GMD0
CKDIR
UFORM
IRS
7 to 0
TI
TXEPT
RI
TE
RE
SOF
TCRCE
ABTE
TBSF1, TBSF0
CMP2E to CMP0E Select whether received data is compared or not
CMP3E
RCRCE
RSHTE
RBSF1, RBSF0
BSERR, ABT
IRF3 to IRF0
7 to 0
7 to 0
7 to 0
7 to 0
15 to 0
15 to 0
7 to 0
7 to 0
7 to 0
7 to 0
CCS1, CCS0
CCS3, CCS2
2
5
C
8 /
Page 319
, 4
Bit
M
3
2
C
f o
8 /
4
4
) T
Select count source
Select divide ratio of count source
Select the base timer interrupt
Set to "0001 0010
Set to "0000 0000
Set to "0000 0000
Set bit rate
Set the timing of the rising edge of the transfer clock.
Timing of the falling edge ("H" width of the transfer clock) is fixed.
Setting value of the G1PO1 register
Set to "00
Set to "11
Set to "11
Set to "0"
Set to "0"
Select how the transmit interrupt is generated
Set to "1111 0110
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Transmit enable bit
Receive enable bit
Set to "0"
Select whether transmit CRC is used or not
Set to "0"
Transmit bit stuffing
Set to "1"
Select whether receive CRC is used or not
Set to "1" to use it in the receiver
Receive bit stuffing
Set to "0"
Select how an interrupt is generated
Write "FE
Data to be compared
Write "7E
Write "01
Transmit CRC calculation result can be read
Receive CRC calculation result can be read
Data, which is output from a transmit data generation circuit, can be read
Set data input to a receive data generation circuit
Received data is stored
For transmission: write data to be transmitted
For reception
Select the HDLC processing clock
Select the HDLC processing clock
9
5
16
16
16
2
2
2
"
"
"
" to abort processing
"
" to abort processing
: received data for comparison is stored
2
2
2
2
"
"
"
"
22. Intelligent I/O (Communication Function)
Function
Setting value of the G1PO0 register
2
"