M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 320

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Table 22.11 SR Waveform Output Mode Specifications
NOTES:
C
Output Waveform
22.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode
1
9
0 .
8 /
B
Output signal level of the OUTC1j pin becomes high ("H") when the value of the base timer matches that
of the G1POj register (j=0, 2, 4, 6). The "H" signal switches to a low-level ("L") signal when the value of the
base timer matches that of the G1POk register (k=j+1) or when the base timer is set to "0000
IVL bit in the G1POCRj register is set to "1" ("H" output as default value), an "H" signal output is provided
when waveform output starts. If the INV bit is set to "1" (output inversed), the level of the output waveform
is inversed. Table 22.11 lists specifications of SR waveform output mode. Figure 22.18 shows an ex-
ample of a SR waveform output mode operation.
1. When the G1PO0 register resets the base timer, the channel 0 and 1 SR waveform generating functions are not
2. When the INV bit in the G1POCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed.
3. Waveform from base timer reset until when output level becomes "H".
4. Waveform from when output level becomes "L" until base timer reset.
0
1
4
0
available.
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Page 297
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4
4
) T
• Free-running operation
• The base timer is cleared to "0000
9
5
(the RST2 and RST1 bits in the G1BCR1 register are set to "00
(1) m < n
(2) m
G1PO0 register
(1) m < n < p+2
(2) m < p+2
(3) If m
"H" width
"L" width
"H" width
"L" width
"H" width
"L" width
"H" width
"L" width
m : setting value of the G1POj register (j=2, 4, 6), 0000
n : setting value of the G1POk register (k=j+1), 0000
p : setting value of the G1PO0 register, 0001
m : setting value of the G1POj register (j=0, 2, 4, 6 )
n : setting value of the G1POk register (k=j+1)
n
p+2, the output level is fixed to "L"
:
:
:
:
:
:
:
:
n
(1)
65536 - m
p + 2 - m
f
f
f
f
m
BT1
m
n-m
f
BT1
(the RST1 bit is set to "1" and the RST2 bit is set to "0")
n-m
f
m
BT1
BT1
m
BT1
f
BT1
f
BT1
BT1
(3)
(3)
22. Intelligent I/O (Waveform Generating Function)
+
+
Specification
16
p + 2 - n
65536 - n
" by matching the base timer with the
f
BT1
f
BT1
(4)
(4)
16
to FFFD
16
16
to FFFF
16
to FFFF
2
")
16
16
16
". If the