M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 232

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
17.2 Clock Asynchronous Serial I/O (UART) Mode
e
E
3
. v
J
2
Table 17.6 UART Mode Specifications
0
Transmit/Receive Control
NOTES:
Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Generation Timing
Error Detect
Selectable Function
C
In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format.
Table 17.6 lists specifications of UART mode.
1
9
0 .
8 /
B
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register remains unchanged
0
1
4
as "1" (interrupt requested).
0
3
G
J
6
u
o r
Item
0 -
. l
u
0
1
, 7
0
p
1
(
2
M
0
0
3
5
2
C
8 /
Page 209
, 4
M
• Character bit (transfer data) : selected from 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selected from odd, even, or none
• Stop bit: selected from 1 bit or 2 bits long
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected):
• The CKDIR bit is set to "1" (external clock selected):
Select from CTS function, RTS function or CTS/RTS function disabled
To start transmitting, the following requirements must be met:
To start receiving, the following requirements must be met:
While transmitting, the following condition can be selected:
While receiving
• Overrun error
• Framing error
• Parity error
• Error sum flag
• LSB first or MSB first
•Serial data logic inverse
•TxD and RxD I/O polarity Inverse
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
3
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- Apply a low-velel ("L") signal to the CTSi pin when the CTS function is selected
- Set the RE bit in the UiC1 register to "1" (receive enable)
- The start bit is detected
- The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register):
- The UiIRS bit is set to "1" (transmission completed):
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
when data transmission from the UARTi transfer register is completed
2
f
f
This error occurs when the bit before the last stop bit of the next received data is read
prior to reading the UiRB register (the first stop bit when selecting 2 stop bits)
This error occurs when the number of stop bits set is not detected
When parity is enabled, this error occurs when the number of "1" in parity and charac-
ter bits does not match the number of "1" set
This flag is set to "1" when any of an overrun, framing or parity errors occur
Data is transmitted or received in either bit 0 or in bit 7
Logic values of data to be transmitted and received data are inversed. The start bit
and stop bit are not inversed
TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
C
j
EXT
/16(m+1) f
f o
8 /
/16(m+1)
4
4
) T
9
5
_______
(2)
j
= f
1
, f
8
, f
2n (1)
f
_______
EXT
: clock applied to the CLKi pin
m
: setting value of the UiBRG register , 00
Specification
_______
_______ _______
_______
17. Serial I/O (UART)
16
to FF
16