M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 432

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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3
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2
xx:
Table 25.4 Software Commands
NOTES:
SRD:
WA:
WD:
BA:
X:
0
C
Read Status Register
Clear Status Register
Erase All Unlocked Block
Read Array
Block Erase
Lock Bit Program
Read Lock Bit Status
1
25.3.5 Software Commands
Read or write 16-bit commands and data from or to even addresses in the user ROM area, in 16-bit units.
When writing a command code, 8 high-order bits (D
Program
9
0 .
B
8 /
1. Blocks 0 to 12 can be erased by the erase all unlocked block command.
0
1
25.3.5.1 Read Array Command
25.3.5.2 Read Status Register Command
25.3.5.3 Clear Status Register Command
4
0
Block A cannot be erased. The block erase command must be used to erase the block A.
The read array command reads the flash memory.
Read array mode is entered by writing command code "xxFF
specified address can be read in 16-bit units after the next bus cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents
from multiple addresses can be read consecutively.
The read status register command reads the SRD register (refer to 25.3.7 Status Register for detail).
By writing command code "xx70
bus cycle. Read an even address in the user ROM area.
Do not execute this command in EW mode 1.
The clear status register command clears the SRD register. By writing "xx50
the FMR07 and FMR06 bits in the FMR0 register are set to "00
register are set to "00
3
J
G
6
8 high-order bits of command code (ignored)
u
Data in the SRD register (D
Address to be written (The address specified in the the first bus cycle is the same even address
16-bit write data
Highest-order block address (must be an even address)
Any even address in the user ROM space
as the address specified in the second bus cycle.)
o r
Command
0 -
. l
u
0
1
, 7
0
p
1
(
2
M
0
0
3
5
2
C
8 /
Page 409
, 4
(1)
M
3
2
2
".
C
f o
8 /
Write
Write
Write
Write
Write
Write
Write
Write
Mode
4
4
7
) T
9
to D
5
0
16
)
First Bus Cycle
" in the first bus cycle, the SRD register can be read in the second
Address
WA
BA
X
X
X
X
X
X
15
(D
xxFF
xxA7
xx70
xx50
xx40
xx20
xx77
xx71
to D
15
Data
to D
8
16
16
16
16
16
16
16
16
) are ignored.
0
)
2
Read
Write
16
Mode
Write
Write
Write
Write
" and the SR5 and SR4 bits in the SRD
" in the first bus cycle. Content of a
Second Bus Cycle
Address
WA
BA
BA
BA
X
16
25. Flash Memory Version
X
" in the first bus cycle,
(D
xxD0
xxD0
xxD0
xxD0
15
SRD
Data
WD
to D
16
16
16
16
0
)