M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 154

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
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12. Watchdog Timer
e
E
3
. v
J
2
Figure 12.1 Watchdog Timer Block Diagram
0
C
The watchdog timer monitors the program executions and detects defective program. It allows the micro-
computer to trigger a reset or to generate an interrupt if the program error occurs. The watchdog timer
contains a 15-bit counter, which is decremented by the CPU clock that the prescaler divides. The CM06 bit
in the CM0 register determines whether a watchdog timer interrupt request or reset is generated if the
watchdog timer underflows. The CM06 bit can only be set to "1" (reset). Once the CM06 bit is set to "1", it
cannot be changed to "0" ( watchdog timer interrupt) by program. The CM06 bit is set to "0" only after reset.
When the main clock, on-chip oscillator clock, or PLL clock runs as the CPU clock, the WDC7 bit in the
WDC register determine whether the prescaler divides the clock by 16 or by 128. When the sub clock runs
as the CPU clock, the prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer
cycle is calculated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock,
When the sub clock is selected as the CPU clock,
For example, if the CPU clock frequency is 30MHz and the prescaler divides it by 16, the watchdog timer
cycle is approximately 17.5 ms.
The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is
generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler
stop after reset. They begin counting when the WDTS register is set.
The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting
from the value held when the mode or state is exited.
Figure 12.1 shows a block diagram of the watchdog timer. Figure 12.2 shows registers associated with the
watchdog timer.
1
9
8 /
0 .
B
HOLD Signal
0
1
4
CPU Clock
0
G
3
J
6
u
o r
0 -
. l
Watchdog timer cycle =
Watchdog timer cycle =
u
0
1
p
, 7
0
1
Write to WDTS Register
(
CM06, CM07 : Bits in the CM0 Register
WDC7 : Bit in the WDC Register
PM22 : Bit in the PM2 Register
2
M
Internal Reset Signal
0
3
0
2
5
C
8 /
Page 131
, 4
M
3
2
C
8 /
f o
4
4
Prescaler
) T
9
1/128
1/16
Divide-by-16 or -128 prescaler x counter value of watchdog timer (32768)
1/2
5
Divide-by-2 prescaler x counter value of watchdog timer (32768)
On-chip Oscillator Clock
CM07 = 0
WDC7 = 0
CM07 = 0
WDC7 = 1
CM07 = 1
PM22 = 1
PM22 = 0
CPU clock
CPU clock
Watchdog Timer
Set to
7FFF
16
CM06 = 0
CM06 = 1
12. Watchdog Timer
Watchdog Timer
Interrupt Request
Reset