M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 502

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
27.8 DMAC
e
E
3
. v
J
2
0
C
1
9
8 /
0 .
B
• Set DMAC-associated registers while the MDi1 and MDi0 bits (i=0 to 3) in the channel to be used are set
• Do not set the DRQ bit in the DMiSL register to "0" (no request).
• To start a DMA transfer by a software trigger, set the DSR bit and DRQ bit in the DMiSL register to "1"
• Do not generate a channel i DMA request when setting the MDi1 and MDi0 bits in the DMDj register
• Select the peripheral function which causes the DMA request after setting the DMA-associated regis-
• Enable DMA
If a DMA request is generated but the receiving channel is not ready to receive
to "00
at the end of setup procedure to start DMA requests.
not occur and the DRQ bit is set to "0".
simultaneously.
(j=0,1) corresponding to channel i to "01
of channel i is set to "1".
ters. If none of the conditions above (setting INT interrupt as DMA request source) apply, do not write
"1" to the DCTi register.
program.
0
1
4
0
G
3
NOTES:
NOTES:
J
6
u
o r
0 -
. l
1. The MDi1 and MDi0 bits are set to "00
e.g.,
2. DMA is enabled when the values set in the MDi1 to MDi0 bits in the DMDj register are changed
2
u
0
1
" (DMA disabled). Set the MDi1 and MDi0 bits to "01
p
, 7
0
times).
from "00
1
(
2
M
0
3
0
2
5
(2)
C
8 /
after setting the DMiSL register (i=0 to 3) and waiting six BCLK cycles or more by
Page 479
2
, 4
" (DMA disabled) to "01
OR.B #0A0h,DMiSL
M
3
2
C
8 /
f o
4
4
) T
9
5
2
" (single transfer) or "11
2
" (single transfer) or "11
______
2
" or the DCTi register is set to "0000
; Set the DSR and DRQ bits to "1" simultaneously
2
" (single transfer) or "11
2
" (repeat transfer), if the DCTi register
2
" (repeat transfer).
(1)
, the DMA transfer does
27. Precautions (DMAC)
2
" (repeat transfer)
16
" (transferred 0