M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 176

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
14.8 Execution Time
e
E
3
. v
J
2
Figure 14.5 Transfer Cycle
0
C
a: If IMM = 0 (source of transfer is immediate data), a = 0;
b: If UPDS = 1 (source transfer address is a relocatable address), b = 0;
c: If UPDD = 1 (destination transfer address is a relocatable address), c = 0;
d: If OPER = 0 (calculation function is not selected), d = 0;
e: If CHAIN = 0 (chained transfer is not selected), e = 0; if CHAIN = 1 (chained transfer is selected), e = 4
m: BRST = 0 (single transfer), m = 1; BRST = 1 (burst transfer), m = the value set in transfer counter
n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1
k: Number of transfers set in the CNT2 to CNT0 bits
DMAC II execution cycle is calculated by the following equations:
Multiple transfers: t = 21+ (11 + b + c) x k cycles
Other than multiple transfers: t = 6 + (26 + a + b + c + d) x m + (4 + e) x n cycles
The equations above are approximations. The number of cycles may vary depending on CPU state, bus
wait state, and DMAC II index allocation.
The first instruction from the end-of-transfer interrupt routine is executed in the eighth cycle after the DMAC
II transfer is completed.
When an interrupt request as a DMAC II transfer request source and another interrupt request with higher
priority (e.g., NMI or watchdog timer) are generated simultaneously, the interrupt with higher priority takes
precedence over the DMAC II transfer. The pending DMAC II transfer starts after the interrupt sequence
has been completed.
1
9
0 .
8 /
B
if IMM = 1 (source of transfer is memory), a = –1
if UPDS = 0 (source transfer address is a fixed address), b = 1
if UPDD = 0 (destination transfer address is a fixed address), c = 1
if OPER = 1 (calculation function is selected) and UPDS = 0 (source of transfer is immediate data or fixed
if OPER = 1 (calculation function is selected) and UPDS = 1 (source of transfer is relocatable address
0
1
memory), d = 8
4
Program
0
If the end-of-transfer interrupt (transfer counter = 2) occurs with no chained transfer function
after a memory-to-memory transfer occurs with a relocatable source address, fixed destination address,
single transfer and double transfer:
3
G
J
Transfer counter = 2
6
u
o r
0 -
. l
First DMAC II transfer
Second DMAC II transfer t=6+26x1+4x0=32 cycles
a=-1
address memory), d = 7;
DMAC II transfer request
u
0
1
p
, 7
0
1
(
2
M
_______
0
3
0
DMAC II transfer
2
b=0
5
C
(First time)
36
8 /
Page 153
cycles
Decrement a transfer counter
Transfer counter = 1
, 4
M
c=1
3
2
C
f o
8 /
4
4
t=6+26x1+4x1=36 cycles
d=0
) T
9
5
Program
Transfer counter = 1
e=0
DMAC II transfer request
DMAC II transfer
m=1
(Second time)
32
cycles
Decrement a transfer counter
Transfer counter = 0
7
cycles
Processing the end-of-transfer
interrupt
14. DMACII