M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 263

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
17.7 Special Mode 5 (SIM Mode)
e
E
3
. v
J
2
Table 17.34 SIM Mode Specifications
0
NOTES:
C
In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are
available and a low-level ("L") signal output can be provided from the TxDi pin (i=0 to 4) when a parity error
is detected.
Table 17.34 lists specifications of SIM mode. Table 17.35 lists register settings. Tables 17.36 to 17.38 list
pin settings.
Transfer Clock
Transmit/Receive Control
Other Setting Items
Transmit Start Condition To start transmitting, the following requirements must be met:
Receive Start Condition To start receiving, the following requirements must be met:
Interrupt Request
Generation Timing
Error Detection
1
Transfer Data Format
9
8 /
0 .
B
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
0
1
4
0
"1" (interrupt requested).
G
3
J
6
u
Item
o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
3
0
2
5
C
8 /
Page 240
, 4
Transfer format:
• The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected):
Do not set the CKDIR bit to "1" (external clock selected)
The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled)
The UiIRS bit in the UiC1 register is set to "1" (transmission completed)
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Detect the start bit
• While transmitting,
• While receiving,
• Overrun error
• Flaming error
• Parity error
• Error sum flag
M
• Transfer data: 8-bit UART mode
• In direct format
Parity:
Data logic:
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
-The UiIRS bit is set to "1" (transmission completed):
3
when data transmission from the UARTi transfer register is completed
This error occurs when the eighth bit of the next data is received before reading the
UiRB register
This error occurs when the number of the stop bit set is not detected
This error occurs when the number of "1" in parity bit and character bits differs from
the number set
The SUM bit is set to "1" when an overrun error, framing error or parity error occurs
2
C
f
j
8 /
/16(m+1)
f o
4
4
) T
9
5
(1)
(1)
Even
Direct
LSB first
f
j
= f
1
, f
8
, f
2n (2)
m
: setting value of the UiBRG register, 00
Transfer format:
Specification
• One stop bit
• In inverse format
Parity:
Data logic:
_______
_______
17. Serial I/O (Special Function)
Odd
Inverse
MSB first
16
to FF
16