M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 336

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
Figure 22.30 Transmit and Receive Operation
0
C
1
9
0 .
8 /
B
0
1
4
(2) When the Communication Clock is Generated in Channel 3 Phase-Delayed Waveform Output Mode
0
(1) When the Commumictin Clock is Set to f
3
G
J
6
external clock
Transfer clock
ISTxDi pin Output
(data to be transmitted)
SIOiTR bit
when IRS=0
(no data in the
SIOiTR bit
when IRS=1
(transmission completed)
ISRxDi pin Input
(received data)
SIOiRR bit
Base Timer
ISCLK1 pin Output
(transmit clock in the
channel 3 generating
function)
ISTxD1 pin Output
(data to be transmitted)
SIO1TR bit
when IRS=0
(no data in the
ISRxD1 pin Input
(received data)
SIO1RR bit
u
TE bit
GiTB register)
G1TB register)
o r
(Communication Units 0 and 1)
(Communication Unit 1)
0 -
. l
u
0
1
f
p
, 7
0
8
, f
The above applies to the following conditions:
The above applies to the following conditions:
1
(
2n
2
M
• The CKDIR bit in the GiMR register is set to "0" (internal clock)
• The CCS1 and CCS0 bits or the CCS3 and CCS2 bits in the CCS register
• The UFORM bit in the GiMR register is set to "0" (LSB first)
• The IPOL and OPOL bits in the GiCR register are set to "0" (no inverse)
• The CKDIR bit in the G1MR register is set to "0" (internal clock)
• The CCS3 and CCS2 bits in the CCS register are set to "00
• The UFORM bit in the G1MR register is set to "0" (LSB first)
• The IPOL and OPOL bits in the G1CR register are set to "0" (no inverse)
0
or
are set to "10
3
0
2
5
C
Write to the GiTB register
"1"
"0"
8 /
Page 313
Write to the G1TB register
, 4
m
n+2
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
M
2
" or "11
3
2
C
2
f o
8 /
"
4
4
) T
9
Bit 0
Bit 0
Bit 0
Bit 0
5
Write "0" by program
if setting to "0"
The base timer is reset by the channel 0
waveform generating function
Write "0" by program
if setting to "0"
8
Bit 1
Bit 1
Bit 1
, f
Bit 1
2n
or External Clock
2
"
Bit 2
Bit 2
Bit 2
Bit 2
22. Intelligent I/O (Communication Function)
SIOiTR bit : Bit in the IIOjIR register (j=1, 3)
SIOiRR bit : Bit in the IIOkIR register (k=0, 2)
IRS bit
TE bit
i=0, 1
n : Setting value of the G1PO0 register
m : Setting value of the G1PO3 register
SIO1TR bit : Bit in the IIO3IR register
SIO1RR bit : Bit in the IIO2IR register
IRS bit
Bit 6
Bit 6
Bit 6
Bit 6
Write "0" by program if setting to "0"
Write "0" by program if setting to "0"
: Bit in the GiCR register
: Bit in the GiMR register
: Bit in the G1MR register
Bit7
Bit7
Bit7
Bit 7
Write "0" by program
if setting to "0"